Patents by Inventor Ralph Oberhuber
Ralph Oberhuber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8624661Abstract: A non-linear correction current ICTAT2 (current complementary to the square of absolute temperature) is generated from a current IPTAT (current proportional to absolute temperature) and a current ICTAT (current complementary to absolute temperature), both modified in a circuit having a topology and components which capitalize on the logarithmic relationship between transistor collector current and base-emitter voltage. The resulting ICTAT2 current (current complementary to the square of absolute temperature) is injected into a node of a bandgap reference circuit to compensate for non-linear temperature effects on output voltage. A more general correction circuit generates both IPTAT2 and ICTAT2, and applies each to a respective multiplier which, in a preferred embodiment, is a current DAC configured as a multiplier.Type: GrantFiled: December 21, 2007Date of Patent: January 7, 2014Assignee: Texas Instruments IncorporatedInventors: Ralph Oberhuber, Keith Brouse
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Patent number: 7710190Abstract: An apparatus for compensating temperature changes in a temperature associated with a compensated device includes: (a) An input circuit having a first input locus for receiving a temperature-indicating signal and a second input locus for receiving a sign-indicating signal. The temperature-indicating signal indicates magnitude of the temperature. The sign-indicating signal indicates a first sign when a control signal is greater than a predetermined value and indicates a second sign when the control signal is less than the predetermined value.Type: GrantFiled: August 10, 2006Date of Patent: May 4, 2010Assignee: Texas Instruments IncorporatedInventor: Ralph Oberhuber
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Patent number: 7696909Abstract: An apparatus for adjusting a first signal with respect to a second signal includes: (a) A first converter receiving the first signal and employing n first converting elements for digitally converting the first signal to at least one first signal element. (b) A second converter coupled with an output, receiving the second signal and employing n second converting elements for digitally converting the second signal to a second representative signal presented at the output. (c) An adjusting element coupled with each of selected of the first converting elements. Each adjusting element is coupled with the output and cooperates with the connected selected element to present a corrected signal element to the output. The output presents an aggregate output signal including contributions from the second representative signal and each corrected signal element. Adjusting is effected by altering at least one corrected first signal element presented to the output.Type: GrantFiled: August 23, 2006Date of Patent: April 13, 2010Assignee: Texas Instruments IncorporatedInventor: Ralph Oberhuber
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Patent number: 7541872Abstract: A multi-stage circuit has a first stage powered by the output voltage of a next stage. A current source within the first stage provides a tail current for a differential amplifier within the first stage. When the first stage has an operating voltage high enough for proper operation, this tail current is at a nominal level; if the voltage is too low for proper operation of the first stage, the tail current is below this nominal level. A comparator, which has one input coupled to a node within this current source, a second input coupled to a threshold voltage, and an output coupled to a control node within the next stage, provides an output indicative of whether or not the tail current is substantially at its nominal level.Type: GrantFiled: December 21, 2007Date of Patent: June 2, 2009Assignee: Texas Instruments IncorporatedInventor: Ralph Oberhuber
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Patent number: 7508027Abstract: The invention relates to a single-poly EPROM comprising a source, a drain, a control gate, a floating gate and an additional gate. The control gate is positioned laterally of a channel between the source and the drain. The floating gate is positioned above the channel above the control gate. The additional gate is positioned above the floating gate, wherein the additional gate is electrically connected to the control gate.Type: GrantFiled: August 28, 2006Date of Patent: March 24, 2009Assignee: Texas Instruments IncorporatedInventors: Ralph Oberhuber, Reiner Jumpertz
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Publication number: 20090015332Abstract: A multi-stage circuit has a first stage powered by the output voltage of a next stage. A current source within the first stage provides a tail current for a differential amplifier within the first stage. When the first stage has an operating voltage high enough for proper operation, this tail current is at a nominal level; if the voltage is too low for proper operation of the first stage, the tail current is below this nominal level. A comparator, which has one input coupled to a node within this current source, a second input coupled to a threshold voltage, and an output coupled to a control node within the next stage, provides an output indicative of whether or not the tail current is substantially at its nominal level.Type: ApplicationFiled: December 21, 2007Publication date: January 15, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Ralph Oberhuber
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Patent number: 7436701Abstract: A single poly EPROM comprises a floating gate (10), a control gate (12), a source (16) and a drain (18). The control gate (12) is positioned laterally of a channel between the source (16) and the drain (18). The floating gate (10) is positioned above the channel and above the control gate (12). The single poly EPROM device further comprises an additional gate (40) above the floating gate (10) and a control. The control is connected to the additional gate (40) for controlling a voltage at the floating gate (10) in order to prevent the floating gate (10) from being unintentionally charged or discharged.Type: GrantFiled: December 21, 2005Date of Patent: October 14, 2008Assignee: Texas Instruments incorporatedInventor: Ralph Oberhuber
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Publication number: 20080164938Abstract: A non-linear correction current ICTAT2 (current complementary to the square of absolute temperature) is generated from a current IPTAT (current proportional to absolute temperature) and a current ICTAT (current complementary to absolute temperature), both modified in a circuit having a topology and components which capitalize on the logarithmic relationship between transistor collector current and base-emitter voltage. The resulting ICTAT2 current (current complementary to the square of absolute temperature) is injected into a node of a bandgap reference circuit to compensate for non-linear temperature effects on output voltage. A more general correction circuit generates both IPTAT2 and ICTAT2, and applies each to a respective multiplier which, in a preferred embodiment, is a current DAC configured as a multiplier.Type: ApplicationFiled: December 21, 2007Publication date: July 10, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Ralph Oberhuber, Keith Brouse
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Publication number: 20080061864Abstract: An apparatus for adjusting a first signal with respect to a second signal includes: (a) A first converter receiving the first signal and employing n first converting elements for digitally converting the first signal to at least one first signal element. (b) A second converter coupled with an output, receiving the second signal and employing n second converting elements for digitally converting the second signal to a second representative signal presented at the output. (c) An adjusting element coupled with each of selected of the first converting elements. Each adjusting element is coupled with the output and cooperates with the connected selected element to present a corrected signal element to the output. The output presents an aggregate output signal including contributions from the second representative signal and each corrected signal element. Adjusting is effected by altering at least one corrected first signal element presented to the output.Type: ApplicationFiled: August 23, 2006Publication date: March 13, 2008Inventor: Ralph Oberhuber
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Publication number: 20080036524Abstract: An apparatus for compensating temperature changes in a temperature associated with a compensated device includes: (a) An input circuit having a first input locus for receiving a temperature-indicating signal and a second input locus for receiving a sign-indicating signal. The temperature-indicating signal indicates magnitude of the temperature. The sign-indicating signal indicates a first sign when a control signal is greater than a predetermined value and indicates a second sign when the control signal is less than the predetermined value.Type: ApplicationFiled: August 10, 2006Publication date: February 14, 2008Inventor: Ralph Oberhuber
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Publication number: 20070048939Abstract: The invention relates to a single-poly EPROM comprising a source, a drain, a control gate, a floating gate and an additional gate. The control gate is positioned laterally of a channel between the source and the drain. The floating gate is positioned above the channel above the control gate. The additional gate is positioned above the floating gate, wherein the additional gate is electrically connected to the control gate.Type: ApplicationFiled: August 28, 2006Publication date: March 1, 2007Inventors: Ralph Oberhuber, Reiner Jumpertz
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Patent number: 7166903Abstract: Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate layer (16) and first and second lateral sides. The first capacitor structure overlies a channel region of a first conductivity type in a semiconductor substrate (4). A second capacitor structure comprising a second dielectric layer (26) and a second gate layer (28) is formed overlying the first gate structure. A source region (22) of a second conductivity type formed in the semiconductor substrate (6) proximate the first lateral side of the gate and a drain extension region/well (12) lightly doped of the second conductivity type is formed in the semiconductor substrate under a portion of the gate structure. A drain region (24) of the second conductivity type formed within the drain extension region (12). The first capacitor structure and the second capacitor structure connect in series to permit a higher operational gate voltage.Type: GrantFiled: April 7, 2006Date of Patent: January 23, 2007Assignee: Texas Instruments IncorporatedInventors: Jozef Mitros, Ralph Oberhuber
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Patent number: 7157784Abstract: Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate layer (16) and first and second lateral sides. The first capacitor structure overlies a channel region of a first conductivity type in a semiconductor substrate (4). A second capacitor structure comprising a second dielectric layer (26) and a second gate layer (28) is formed overlying the first gate structure. A source region (22) of a second conductivity type formed in the semiconductor substrate (6) proximate the first lateral side of the gate and a drain extension region/well (12) lightly doped of the second conductivity type is formed in the semiconductor substrate under a portion of the gate structure. A drain region (24) of the second conductivity type formed within the drain extension region (12). The first capacitor structure and the second capacitor structure connect in series to permit a higher operational gate voltage.Type: GrantFiled: January 31, 2005Date of Patent: January 2, 2007Assignee: Texas Instruments IncorporatedInventors: Jozef Mitros, Ralph Oberhuber
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Publication number: 20060175678Abstract: Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate layer (16) and first and second lateral sides. The first capacitor structure overlies a channel region of a first conductivity type in a semiconductor substrate (4). A second capacitor structure comprising a second dielectric layer (26) and a second gate layer (28) is formed overlying the first gate structure. A source region (22) of a second conductivity type formed in the semiconductor substrate (6) proximate the first lateral side of the gate and a drain extension region/well (12) lightly doped of the second conductivity type is formed in the semiconductor substrate under a portion of the gate structure. A drain region (24) of the second conductivity type formed within the drain extension region (12). The first capacitor structure and the second capacitor structure connect in series to permit a higher operational gate voltage.Type: ApplicationFiled: April 7, 2006Publication date: August 10, 2006Inventors: Jozef Mitros, Ralph Oberhuber
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Publication number: 20060170055Abstract: Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate layer (16) and first and second lateral sides. The first capacitor structure overlies a channel region of a first conductivity type in a semiconductor substrate (4). A second capacitor structure comprising a second dielectric layer (26) and a second gate layer (28) is formed overlying the first gate structure. A source region (22) of a second conductivity type formed in the semiconductor substrate (6) proximate the first lateral side of the gate and a drain extension region/well (12) lightly doped of the second conductivity type is formed in the semiconductor substrate under a portion of the gate structure. A drain region (24) of the second conductivity type formed within the drain extension region (12). The first capacitor structure and the second capacitor structure connect in series to permit a higher operational gate voltage.Type: ApplicationFiled: January 31, 2005Publication date: August 3, 2006Inventors: Jozef Mitros, Ralph Oberhuber
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Publication number: 20060133151Abstract: The present invention relates to a single poly EPROM device. The single poly EPROM comprises a floating gate (10), a control gate (12), a source (16) and a drain (18). The control gate (12) is positioned laterally of a channel between the source (16) and the drain (18). The floating gate (10) is positioned above the channel and above the control gate (12). The single poly EPROM device further comprises an additional gate (40) above the floating gate (10) and a control. The control is connected to the additional gate (40) for controlling a voltage at the floating gate (10) in order to prevent the floating gate (10) from being unintentionally charged or discharged.Type: ApplicationFiled: December 21, 2005Publication date: June 22, 2006Inventor: Ralph Oberhuber
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Patent number: 7060556Abstract: Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate layer (16) and first and second lateral sides. The first capacitor structure overlies a channel region of a first conductivity type in a semiconductor substrate (4). A second capacitor structure comprising a second dielectric layer (26) and a second gate layer (28) is formed overlying the first gate structure. A source region (22) of a second conductivity type formed in the semiconductor substrate (6) proximate the first lateral side of the gate and a drain extension region/well (12) lightly doped of the second conductivity type is formed in the semiconductor substrate under a portion of the gate structure. A drain region (24) of the second conductivity type formed within the drain extension region (12). The first capacitor structure and the second capacitor structure connect in series to permit a higher operational gate voltage.Type: GrantFiled: January 12, 2006Date of Patent: June 13, 2006Assignee: Texas Instruments IncorporatedInventors: Jozef Mitros, Ralph Oberhuber
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Patent number: 6982627Abstract: A transponder (1) comprising an antenna (4), a demodulator (5) and a signal processing circuit (6) which converts a modulated signal received via the antenna (4) into a signal suitable for processing in the demodulator (5). The signal processing circuit (6) comprises an amplifier (7) with a predefined amplification factor and a closed loop control circuit (8) serving to maintain the voltage swing of the processed signal applied at the input of the demodulator (5) substantially constant. In a preferred embodiment the closed loop control circuit comprises a capacitor which is continually discharged and differingly charged as a function of the strength of the output signal of the amplifier of the signal processing circuit, the voltage resulting across the capacitor controlling a controllable resistor connected in parallel to the input of the signal processing circuit and forming with a coupling capacitor a voltage divider.Type: GrantFiled: June 13, 2003Date of Patent: January 3, 2006Assignee: Texas Instruments IncorporatedInventors: Ralph Oberhuber, Wolfgang Steinhagen, Franz Prexl
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Patent number: 6894542Abstract: A comparator with hysteresis which achieves fast switching despite a low current consumption. The comparator comprises a first transistor (M1) and a second transistor (M2) whose gates form the inputs of the comparator. The main current paths of both transistors are connected to each other at one end, with a third transistor (M3) and a fourth transistor (M4) being provided. The gate of the third transistor is connected to the gate of the first transistor and its main current path is circuited between the one end of the main current paths of the first and second transistor and is connected via the main current path of the fourth transistor to the other end of the main current path of the second transistor. The gate of the fourth transistor is connected to the output signal or inverted output signal of the comparator. The comparator in accordance with the invention may be put to use e.g. in an ASK demodulator such as those used in RFID transponders.Type: GrantFiled: July 11, 2003Date of Patent: May 17, 2005Assignee: Texas Instruments Deutschland, GmbHInventors: Franz Prexl, Wolfgang Steinhagen, Ralph Oberhuber, Kaiser Ulrich
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Patent number: 6861901Abstract: A voltage follower comprising a first field-effect transistor (MN1) whose gate forms the input of the voltage follower. Further provided is a second field-effect transistor (MN2) whose drain connected to the gate forms the output of the voltage follower. The sources of the two field-effect transistors (MN1, MN2) are connected to each other and to the drain of a third field-effect transistor (MN3) serving as current source and to the gate of which a predefined bias voltage is applied. The invention employs in addition a fourth field-effect transistor (MN4) whose source-drain path is circuited between the output of the voltage follower and the drain of the third field-effect transistor (MN3) and whose gate is connected to the gate of the third field-effect transistor (MN3). As compared to prior art voltage followers the voltage follower in accordance with the invention comprises a wider voltage range in which it can be put to use. This can be made use of e.g.Type: GrantFiled: June 12, 2003Date of Patent: March 1, 2005Assignee: Texas Instruments Deutschland, GmbHInventors: Franz Prexl, Wolfgang Steinhagen, Ralph Oberhuber