Abstract: A disk array controller includes a local microprocessor, a bus master interface, a compatible interface, buffer memory and a disk interface. The controller includes a DMA controller between the microprocessor, the bus master interface, the compatibility interface and the buffer memory. DMA controllers are also provided between the disk interface and the buffer memory. One of these DMA channels includes an XOR engine used to develop parity information used with the disk array. The various DMA controllers are cycled to allow access to the buffer memory and the disk interface. A posted write memory system is connected as a selectable disk drive to the disk interface. The posted write memory system includes mirrored, parity checked and battery backed semiconductor memory to allow posted write data to be retained during power down conditions with only a very small change of data loss.

Abstract: In a desktop computer, a hard disk drive activity indicator such as an LED is mounted on the front panel, remote from its associated hard disk drive which is mounted in the back of the housing. The LED is triggered in response both I/O writes for addresses reserved for use with the hard disk, and interrupt requests generated by the hard disk drive. Triggering logic on the motherboard of the computer detects these conditions, and a retriggerable monostable multivibrator which activates the LED. The LED is coupled to the triggering logic with by a conductor that need not be added as an additional part or assembly but instead is within an already-existing assembly such as the power supply.

Abstract: An interface between a CPU bus and peripheral device such as a standard embedded controller disk drive uses either a dedicated, I/O mapped register set for control and status communication between the host CPU and the disk controller, or an alternate "flex mode" protocol which allows the drive to be used with great versatility in a wide variety of systems. This alternate "flex mode" protocol does not require changes to the hardware definition of the drive interface, but instead uses the data port to transfer information blocks to set up a subsequent data transfer through this port.