Patents by Inventor Ralph Sanchez
Ralph Sanchez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9939488Abstract: Automated test procedures, carried out under software control, can be employed to test a device, testing individual pins, and/or groups of pins, to detect and diagnose or characterize various types of failures. A distributed FA system includes a shared database for device definitions, test setups, and test results. Test platforms provide I/O curve tracing which can provide both a qualitative visual representation and a quantitative measured performance. The disclosed system enables and exploits front line testing of devices in the field. Response to the customer can be nearly immediate. Eliminate “false returns” by differentiation of use versus a real quality issue.Type: GrantFiled: December 8, 2014Date of Patent: April 10, 2018Assignee: TESEDA CORPORATIONInventors: Joseph M. Salazar, Rich Ackerman, John Raykowski, Armagan Akar, Ralph Sanchez
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Patent number: 9659136Abstract: Various embodiments related to identifying a candidate defect region in a semiconductor device are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; generating a physical representation of portion of a logical design of the semiconductor device, the physical representation including location information for physical instantiations of logical cells and logical interconnections included in the portion of the logical design; identifying a suspect logical region in the physical representation, the suspect logical region including a portion of the logical cells and the logical interconnections electrically connected with the scan chain; generating a candidate defect region within the semiconductor device, the candidate defect region being defined, via the physical representation, to include the physical instantiations of logical cells and logical interconnections included in the suspect logical region; and displaying the candidate defect region.Type: GrantFiled: June 1, 2011Date of Patent: May 23, 2017Assignee: Teseda CorporationInventors: Armagan Akar, Ralph Sanchez
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Publication number: 20150149106Abstract: Automated test procedures, carried out under software control, can be employed to test a device, testing individual pins, and/or groups of pins, to detect and diagnose or characterize various types of failures. A distributed FA system includes a shared database for device definitions, test setups, and test results. Test platforms provide I/O curve tracing which can provide both a qualitative visual representation and a quantitative measured performance. The disclosed system enables and exploits front line testing of devices in the field. Response to the customer can be nearly immediate. Eliminate “false returns” by differentiation of use versus a real quality issue.Type: ApplicationFiled: December 8, 2014Publication date: May 28, 2015Inventors: Joseph M. Salazar, Rich Ackerman, John Raykowski, Armagan Akar, Ralph Sanchez
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Patent number: 8918753Abstract: Various embodiments related to correlating a location of a defect on a substrate for a semiconductor device to an electrical significance of a device structure at that location are disclosed. For example, one embodiment includes receiving a defect location for the location on the substrate where the defect was detected; receiving a physical representation of the semiconductor device for the defect location; generating a significance determination indicating whether the defect is located in an electrically significant region by correlating the defect location to logical and physical layout information included in the physical representation; and displaying the significance determination.Type: GrantFiled: September 12, 2013Date of Patent: December 23, 2014Assignee: Teseda CorporationInventors: Armagan Akar, Ralph Sanchez
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Publication number: 20140115551Abstract: Various embodiments related to correlating a location of a defect on a substrate for a semiconductor device to an electrical significance of a device structure at that location are disclosed. For example, one embodiment includes receiving a defect location for the location on the substrate where the defect was detected; receiving a physical representation of the semiconductor device for the defect location; generating a significance determination indicating whether the defect is located in an electrically significant region by correlating the defect location to logical and physical layout information included in the physical representation; and displaying the significance determination.Type: ApplicationFiled: September 12, 2013Publication date: April 24, 2014Applicant: Teseda CorporationInventors: Armagan Akar, Ralph Sanchez
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Patent number: 8626460Abstract: A chip diagnostics management system includes secure design information that define production features of integrated circuit devices and are accessible according to selected levels of access privilege. A database of device defect information includes information of defects of devices produced according to the production features of the design information and associated wafers, production lots, and dies in or with which the devices were produced. A diagnostic manager correlates device defect information from plural wafers with the design information to identify a device location with a probability of being associated with the device defect information. A diagnostic manager viewer indicates the device location together with an amount of design information correlated the level of access privilege assigned to a selected user.Type: GrantFiled: April 2, 2007Date of Patent: January 7, 2014Assignee: Teseda CorporationInventors: Bruce Kaufman, Ralph Sanchez, Brian Mason
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Patent number: 8539389Abstract: Various embodiments related to correlating a location of a defect on a substrate for a semiconductor device to an electrical significance of a device structure at that location are disclosed. For example, one embodiment includes receiving a defect location for the location on the substrate where the defect was detected; receiving a physical representation of the semiconductor device for the defect location; generating a significance determination indicating whether the defect is located in an electrically significant region by correlating the defect location to logical and physical layout information included in the physical representation; and displaying the significance determination.Type: GrantFiled: June 1, 2011Date of Patent: September 17, 2013Assignee: Teseda CorporationInventors: Armagan Akar, Ralph Sanchez
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Patent number: 8453088Abstract: Various embodiments related to identifying regions including physical defects in semiconductor devices are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; identifying a suspect logical region including a plurality of logic cones electrically connected with the scan chain; adjusting a scope of the suspect logical region by simulating data flow within the logic cones, generating simulated scan chain output based on the simulated data flow within the logic cones, and excluding at least one of the logic cones from the suspect logical region based on a comparison of the electrical test mismatch and the simulated scan chain output; after adjusting the scope of the suspect logical region, generating a candidate defect region, the candidate defect region being defined to include physical instantiations of logical cells and logical interconnections included in the suspect logical region; and displaying the candidate defect region.Type: GrantFiled: June 1, 2011Date of Patent: May 28, 2013Assignee: Teseda CorporationInventors: Armagan Akar, Ralph Sanchez
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Publication number: 20120079442Abstract: Various embodiments related to correlating a location of a defect on a substrate for a semiconductor device to an electrical significance of a device structure at that location are disclosed. For example, one embodiment includes receiving a defect location for the location on the substrate where the defect was detected; receiving a physical representation of the semiconductor device for the defect location; generating a significance determination indicating whether the defect is located in an electrically significant region by correlating the defect location to logical and physical layout information included in the physical representation; and displaying the significance determination.Type: ApplicationFiled: June 1, 2011Publication date: March 29, 2012Applicant: TESEDA CORPORATIONInventors: Armagan Akar, Ralph Sanchez
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Publication number: 20120079439Abstract: Various embodiments related to identifying a candidate defect region in a semiconductor device are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; generating a physical representation of portion of a logical design of the semiconductor device, the physical representation including location information for physical instantiations of logical cells and logical interconnections included in the portion of the logical design; identifying a suspect logical region in the physical representation, the suspect logical region including a portion of the logical cells and the logical interconnections electrically connected with the scan chain; generating a candidate defect region within the semiconductor device, the candidate defect region being defined, via the physical representation, to include the physical instantiations of logical cells and logical interconnections included in the suspect logical region; and displaying the candidate defect region.Type: ApplicationFiled: June 1, 2011Publication date: March 29, 2012Applicant: TESEDA CORPORATIONInventors: Armagan Akar, Ralph Sanchez
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Publication number: 20120079440Abstract: Various embodiments related to identifying regions including physical defects in semiconductor devices are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; identifying a suspect logical region including a plurality of logic cones electrically connected with the scan chain; adjusting a scope of the suspect logical region by simulating data flow within the logic cones, generating simulated scan chain output based on the simulated data flow within the logic cones, and excluding at least one of the logic cones from the suspect logical region based on a comparison of the electrical test mismatch and the simulated scan chain output; after adjusting the scope of the suspect logical region, generating a candidate defect region, the candidate defect region being defined to include physical instantiations of logical cells and logical interconnections included in the suspect logical region; and displaying the candidate defect region.Type: ApplicationFiled: June 1, 2011Publication date: March 29, 2012Applicant: TESEDA CORPORATIONInventors: Armagan Akar, Ralph Sanchez
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Publication number: 20100332172Abstract: A chip diagnostics management system includes secure design information that define production features of integrated circuit devices and are accessible according to selected levels of access privilege. A database of device defect information includes information of defects of devices produced according to the production features of the design information and associated wafers, production lots, and dies in or with which the devices were produced. A diagnostic manager correlates device defect information from plural wafers with the design information to identify a device location with a probability of being associated with the device defect information. A diagnostic manager viewer indicates the device location together with an amount of design information correlated the level of access privilege assigned to a selected user.Type: ApplicationFiled: April 2, 2007Publication date: December 30, 2010Inventors: Bruce Kaufman, Ralph Sanchez, Brian Mason
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Publication number: 20080068561Abstract: A method, system and device for detecting an ocular dysfunction with optic neuropathy, such as the glaucoma group of diseases. More particularly, one eye is exposed to a series of flashes, and the resulting pupillary reflexes of both eyes are measured. The pupillary reflexes can then be evaluated to determine if the ocular dysfunction is present. A device that includes at least one light source can be incorporated into a system for recording and evaluating the pupillary reflexes.Type: ApplicationFiled: October 16, 2007Publication date: March 20, 2008Inventors: Gillray Kandel, Martin Kaback, Ralph Sanchez