Abstract: An analyzer for measuring a sample includes a display, measurement hardware configured to perform a quality control measurement on a vial containing a quality control (QC) sample, and a controller. The controller is in communication with the display and the measurement hardware and is configured to communicate, via the display, instructions to implement a QC measurement on a first vial containing a first QC sample. If a result of the QC measurement is within a pre-determined range the first vial passes the QC measurement. If the result of the QC measurement is not within the pre-determined range the first vial fails the QC measurement. If the first vial fails the QC measurement and if a number of times the first vial fails the QC measurement is less than a predetermined number, the controller is configured to communicate, via the display, instructions to repeat the QC measurement on the first vial.

Abstract: An analyzer includes a display, measurement hardware configured to perform a measurement on a sample, and a controller. The controller is in communication with the display and the measurement hardware and is configured to communicate, via the display, a first pre-analytical procedure of the sample prior to measurement of the sample. The controller is also configured to maintain the analyzer in a state associated with the first procedure for an amount of time equal to a time needed for performing the first procedure. After the time needed for performing the first procedure has elapsed, the controller is configured to communicate, via the display, a second pre-analytical procedure of the sample prior to measurement of the sample.

Abstract: An analyzing system includes an analyzer and a server computer in communication with the analyzer via a network. The analyzer includes a first controller that is configured to communicate, via a display, instructions to an operator of the analyzer when a predetermined event occurs in the analyzer. The instructions request confirmation that the operator received training. The first controller is also configured to receive an indication of whether the operator has completed the training, and, when the indication indicates that the operator has completed the training, request, from the server, a confirmation that the operator has completed the training. The server computer is configured to receive the confirmation request from the analyzer, determine a training status of the operator, and communicate the training status to the analyzer. The first controller prevents measurement of a sample if the operator has not completed the training.

Abstract: An analyzer for measuring a sample includes a display, measurement hardware configured to perform a quality control measurement on a vial containing a quality control (QC) sample, and a controller. The controller is in communication with the display and the measurement hardware and is configured to communicate, via the display, instructions to implement a QC measurement on a first vial containing a first QC sample. If a result of the QC measurement is within a pre-determined range the first vial passes the QC measurement. If the result of the QC measurement is not within the pre-determined range the first vial fails the QC measurement. If the first vial fails the QC measurement and if a number of times the first vial fails the QC measurement is less than a predetermined number, the controller is configured to communicate, via the display, instructions to repeat the QC measurement on the first vial.

Abstract: An analyzer includes a display, measurement hardware configured to perform a measurement on a sample, and a controller. The controller is in communication with the display and the measurement hardware and is configured to communicate, via the display, a first pre-analytical procedure of the sample prior to measurement of the sample. The controller is also configured to maintain the analyzer in a state associated with the first procedure for an amount of time equal to a time needed for performing the first procedure. After the time needed for performing the first procedure has elapsed, the controller is configured to communicate, via the display, a second pre-analytical procedure of the sample prior to measurement of the sample.

Abstract: An analyzing system includes an analyzer and a server computer in communication with the analyzer via a network. The analyzer includes a first controller that is configured to communicate, via a display, instructions to an operator of the analyzer when a predetermined event occurs in the analyzer. The instructions request confirmation that the operator received training. The first controller is also configured to receive an indication of whether the operator has completed the training, and, when the indication indicates that the operator has completed the training, request, from the server, a confirmation that the operator has completed the training. The server computer is configured to receive the confirmation request from the analyzer, determine a training status of the operator, and communicate the training status to the analyzer. The first controller prevents measurement of a sample if the operator has not completed the training.

Abstract: In accordance with the principles of the invention, methods, systems, and computer-readable mediums are provided for displaying cellular analysis result data including accessing cellular analysis result data; determining frequency information of a plurality of cell populations from the cellular analysis result data; associating frequency information of each of the plurality of cell populations with a surface elevation point; and displaying an interactive surface plot of the associated frequency information and the surface elevation points.

Abstract: An electronics assembly is provided having a substrate and at least one electronics package supported on the substrate. The electronics package also has electrical circuitry and first and second side surfaces. The assembly further includes a first heat sink device positioned in thermal communication with the first side surface of the electronics package, and a second heat sink device positioned in thermal communication with the second side surface of the electronics package.

Abstract: An electronics assembly is provided having a carrier that provides a controlled height variability between electronics packages and a heat sink device. The electronics assembly includes a substrate and electronics packages connected to the substrate. The assembly also includes a heat sink device positioned in thermal communication with a first side of the electronics packages. The assembly further includes a carrier disposed between the substrate and the heat sink device. The carrier has a resilient wall that biases the electronics packages towards the heat sink device such that a controlled bond line is provided between the first side of the electronics packages and the heat sink device.

Abstract: A fiber optic tester (10) broadly comprises a testing unit (16) to take measurements across two test points (27), a processing unit (18) to locate faults by analyzing the measurements, a switching unit (20) that can connect termination points (13) of a electrical circuit (12) to the test points (27) in a sequence controlled by the processing unit (18), and a fiber unit (22) to test a optical circuit (14). The tester (10) may also include an electrical harness (24) or an optical harness to connect the electrical circuit (12) to the switching unit (20) or the optical circuit (14) to the fiber unit (22). The processing unit (18) is preferably programed with interconnection information of the circuits (12,14) and internal characteristics of the tester (10). Using the interconnection information and the internal characteristics, the processing unit (18) may accurately detect faults within the circuits (12,14).

Abstract: A 3D rendering texture caching scheme that minimizes external bandwidth requirements for texture and increases the rate at which textured pixels are available. The texture caching scheme efficiently pre-fetches data at the main memory access granularity and stores it in cache memory. The data in the main memory and texture cache memory is organized in a manner to achieve large reuse of texels with a minimum of cache memory to minimize cache misses. The texture main memory stores a two dimensional array of texels, each texel having an address and one of N identifiers. The texture cache memory has addresses partitioned into N banks, each bank containing texels transferred from the main memory that have the corresponding identifier. A cache controller determines which texels need to be transferred from the texture main memory to the texture cache memory and which texels are currently in the cache using a least most recently used algorithm.

Abstract: A fiber optic tester (10) broadly comprises a testing unit (16) to take measurements across two test points (27), a processing unit (18) to locate faults by analyzing the measurements, a switching unit (20) that can connect termination points (13) of a electrical circuit (12) to the test points (27) in a sequence controlled by the processing unit (18), and a fiber unit (22) to test a optical circuit (14). The tester (10) may also include an electrical harness (24) or an optical harness to connect the electrical circuit (12) to the switching unit (20) or the optical circuit (14) to the fiber unit (22). The processing unit (18) is preferably programed with interconnection information of the circuits (12,14) and internal characteristics of the tester (10). Using the interconnection information and the internal characteristics, the processing unit (18) may accurately detect faults within the circuits (12,14).

Abstract: A fiber optic tester (10) broadly comprises a testing unit (16) to take measurements across two test points (27), a processing unit (18) to locate faults by analyzing the measurements, a switching unit (20) that can connect termination points (13) of a electrical circuit (12) to the test points (27) in a sequence controlled by the processing unit (18), and a fiber unit (22) to test a optical circuit (14). The tester (10) may also include an electrical harness (24) or an optical harness to connect the electrical circuit (12) to the switching unit (20) or the optical circuit (14) to the fiber unit (22). The processing unit (18) is preferably programed with interconnection information of the circuits (12, 14) and internal characteristics of the tester (10). Using the interconnection information and the internal characteristics, the processing unit (18) may accurately detect faults within the circuits (12, 14).

Abstract: A fiber optic tester (10) broadly comprises a testing unit (16) to take measurements across two test points (27), a processing unit (18) to locate faults by analyzing the measurements, a switching unit (20) that can connect termination points (13) of a electrical circuit (12) to the test points (27) in a sequence controlled by the processing unit (18), and a fiber unit (22) to test a optical circuit (14). The tester (10) may also include an electrical harness (24) or an optical harness to connect the electrical circuit (12) to the switching unit (20) or the optical circuit (14) to the fiber unit (22). The processing unit (18) is preferably programed with interconnection information of the circuits (12, 14) and internal characteristics of the tester (10). Using the interconnection information and the internal characteristics, the processing unit (18) may accurately detect faults within the circuits (12, 14).

Abstract: A method and apparatus for providing rendering of subsections of screen space receives render commands associated with different screen subsections, such as from a command buffer populated by a coprocessor, and determines which screen section is currently being rendered by a rendering engine, or stated another way, which screen section the host processor wishes to have rendered, and evaluates screen subsection data that is associated with a received rendering command. The screen subsection data identifies a screen subsection for which the command refers. The method includes executing the command if it is determined that the command refers to a current screen section being rendered.

Abstract: An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.

Abstract: An apparatus and method for single instruction multiple data caching includes a memory access request generator operative to receive a primary access request. The method and apparatus further includes a cache controller coupled to the memory access request generator, wherein the cache controller is operative to execute a memory request. The method and apparatus further includes a memory interface coupled to the cache controller, the memory interface operative to retrieve a plurality of requested data. The method and apparatus further includes a request processor coupled to the cache controller, the memory interface and the memory access request generator. The request processor is operative to receive a plurality of requested data and thereupon generate a plurality of parallel data outputs therefrom.

Abstract: A method and apparatus for object-based visibility culling includes receiving a plurality of draw packets, such as pixels or vertices. The method and apparatus further includes comparing each of the plurality of draw packets to a bounding volume object, wherein the bounding volume object may be a low resolution geometric representation of a specific object. Whereupon, for each of the plurality of draw packets, if the draw packet is deemed potentially visible, setting a visibility query identifier and rendering the draw packets having the set visibility query identifier.

Abstract: A fiber optic tester (10) broadly comprises a testing unit (16) to take measurements across two test points (27), a processing unit (18) to locate faults by analyzing the measurements, a switching unit (20) that can connect termination points (13) of a electrical circuit (12) to the test points (27) in a sequence controlled by the processing unit (18), and a fiber unit (22) to test a optical circuit (14). The tester (10) may also include an electrical harness (24) or an optical harness to connect the electrical circuit (12) to the switching unit (20) or the optical circuit (14) to the fiber unit (22). The processing unit (18) is preferably programed with interconnection information of the circuits (12, 14) and internal characteristics of the tester (10). Using the interconnection information and the internal characteristics, the processing unit (18) may accurately detect faults within the circuits (12, 14).

Abstract: A self-compensating fault locator (10) broadly comprises a testing unit (16) to take measurements across two test points (18), a processing unit (20) to locate faults by analyzing the measurements, and a switching unit (22) that can connect termination points (14) of an electrical circuit (12) to the test points (18) in a sequence controlled by the processing unit (20). The fault locator (10) may also include a harness (24) to connect the electrical circuit (12) to the switching unit (22). The processing unit (20) is preferably programed with the electrical circuit's (12) interconnection information. The processing unit (20) also preferably stores internal characteristics of the fault locator (10). Using the interconnection information and the internal characteristics, the processing unit (20) may accurately locate faults within the electrical circuit (12). Additionally, the processing unit (20) may locate faults within the fault locator (10) and/or the harness (24).