Abstract: The invention relates to a phase detector, especially for a Phase Locked Loop of a desynchronizer of a digital transmission system for the transmission of signals of the synchronous digital hierarchy with a difference former (subtractor) connected to a comparator, to which can be conducted at the input side, via a first accumulator, a first input signal, and via a second accumulator a second input signal with the comparator being connected at the output side via a coder to a control input of the second accumulator.

Abstract: The invention relates to a transmission system comprising a control circuit which circuit includes a comparator (18, 19, 20; 25 to 29; 46; 50 to 52, 57 to 60) for comparing a first input signal and a second input signal. For reducing the low-frequency phase error, the comparator (18, 19, 20; 25 to 29; 46; 50 to 52, 57 to 60) is provided for changing the state of a first comparing signal derived from the first input signal and/or the state of a second comparing signal derived from the second input signal, or the state of the output signal resulting from a combination of the two comparing signals at instants denoted by an auxiliary signal whose frequency deviates from the frequency of the signal to be changed.

Abstract: The invention relates to a transmission system comprising at least a transmission device for exchanging transport modules in signals of a synchronous multiplex hierarchy which signals have a frame structure of columns and rows. The transmission device (5) comprises at least an adapter circuit (5) and a switching network (5). The adapter circuit (5) is provided to delay at least a higher-order transport module up to a given position in the adapted frame structured signal. The switching network comprises at least a time stage provided to write and identify column by column the bytes to be stored of an adapted frame structured signal and to read out the bytes identified column by column in a given order to form at least an outgoing frame structured signal.

Abstract: The invention relates to a measuring device for measuring the phase deviation of at least a subordinate transport unit of a synchronous signal transmitted through a synchronous transmission system. The measuring device comprises a transmitter unit for forming the synchronous signal to be transmitted, a first desynchronizer for splitting up the synchronous signal and for detecting at least a given byte of the subordinate transport unit, a second desynchronizer for splitting up the received synchronous signal which has passed through the transmission system and for detecting at least the given byte in the received synchronous signal, and an evaluation unit for calculating the phase deviation from the moments of detection of at least the given byte in the transmitted and the received synchronous signals.

Abstract: The invention relates to a transmission system comprising a synchronizer for forming a multiplex signal, comprising at least a device for conveying the multiplex signal, and a desynchronizer. The desynchronizer comprises at least a buffer store for buffering transport unit data contained in the signal, a write address generator for controlling the writing of the data in the buffer store, a control arrangement for forming a control signal for the write address generator from the signal, a read address generator for controlling the reading of the data from the buffer store, a difference circuit for forming difference values between the addresses of write and read address generators and a generating circuit for generating from the difference values a read clock signal applied to the read address generator.

Abstract: A transmission system for the synchronous digital hierarchy, comprising an adaptation circuit for compensating for phase variations of an STM-N signal. The adaptation circuit (8) comprises a buffer (17, 33), a write address generator (16, 35), a read address generator (18, 44), a justification decision circuit (24, 43) and an output circuit (19, 45), for inserting justification locations for at least one container of the STM-N signal. The buffer is provided for writing and reading the container data. The write address generator is provided for generating write addresses for the data to be written and the read address generator is provided for generating read addresses for the data to be read out. The justification decision circuit is used for forming the mean value of the differences of the addresses of the read and write address generators over a specific period of time and for forming a justification signal as a function of the mean value.

Abstract: A circuit for adjusting the bit rates of two signals is necessary for plesiochronous multiplexers, for example, to bring the plesiochronous signals, which are to be combined to one digital signal of the next higher hierarchy, to the same bit rate. For this purpose, the circuit arrangement comprises an elastic store (4) as well as a justification decision circuit (15, 16). In order that a circuit having such features can be used for bit rates of the order of 140 Mbit/s and yet can be arranged largely in CMOS technology, the bit clocks of the first and second signals are reduced at the ratio of 1:n. Furthermore, a serial-to-parallel converter (2) converts bit groups of n serial bits of a first signal into bit groups of n parallel bits, which are written in groups into the elastic store (4) and are also read out in groups. The parallel bit groups read out are applied to a controllable selection matrix (5) having n outputs, which transmits n selected bits of more than one bit group to n outputs.

Abstract: A digital transmission system having at least one adaptation circuit for compensating for phase variations of a STM-N signal. For inserting justification locations for at least one container of the STM-N signal, the adaptation circuit (8) includes a buffer (17, 51), a write address generator (16, 53), a read address generator (18, 61) a justification decision circuit (24, 60) and an output circuit (19, 62). The buffer stores container data in which justification locations may be inserted. The write address generator provides write addresses for data to be written in the buffer, and the read address generator provides read addresses in the buffer. In one embodiment differences between the read and write address values are combined with justification information which has been low pass filtered. In another embodiment these differences are low pass filtered and used for forming the justification decision signal.

Abstract: A buffer memory, in which a first signal is written and from which a second signal is read out, and a subtractor which forms the difference between the counts of a read counter and a write counter, which control reading and writing. A justification decision circuit generates a stop signal for the read counter. An accumulator accumulates the difference signal over a predetermined time interval. The accumulator output, delayed by a time interval and weighted with a second factor, and a justification signal denoting the number of stuff bits caused by the justification decision circuit between two stop instants, are added to the subtractor output in the accumulator.

Abstract: A circuit arrangement for adapting the bit rates of two signals to each other comprises an elastic store (6). The useful data of a first frame-structured signal are written into this store (6) by means of a write address counter (7) and read out again by means of a read address counter (8). A phase comparator (16) is used for comparing the counts of these counters (7, 8). In order to largely avoid jitter in the signal that has been read, the read address counter (8) and the phase comparator (16) are incorporated in a control circuit that controls the clock for the read address counter (8). In this control circuit the output signal of the phase comparator (16) is the control error. The controlled system (17) of the control circuit consists of a controllable oscillator circuit with whose output signal and read address counter (8) is clocked. In order to avoid stationary phase shifts with a constant frequency shift, a controller (18) having a PI behavior (PI=proportionality and integration) is used.

Abstract: The described circuit arrangement for removing stuff bits from a frame-structured signal which is available in n parallel bits, comprises a memory circuit (2) which is supplied with the parallel bits (1b). The memory circuit (2) is followed by a controllable selection circuit (3) having n outputs (3a). A control circuit (9) produces control signals (9b, 9c), which determine which bits stored in the memory circuit are transported to the n outputs (3a) of the selection circuit (3). The memory circuit (2) comprises only n delay elements by which each of the n parallel bits (1b) is delayed for the duration of one bit. So as to provide that n delay elements will be sufficient, the control circuit (9) is to block at predetermined time intervals the acceptance of new bits in one or a plurality of delay elements.

Abstract: A circuit arrangement for adjusting the bit rates of two signals of which the higher bit rate signal is structured in frames, includes a buffer memory (2), a write counter and a read counter (6, 8) as well as a phase comparator (7) and a control circuit (10). With these modules the bits of the lower bit rate signal are arranged in the frames of the higher bit rate signal. In addition to these bits negative or positive stuff bits are also inserted in the frames. In order to avoid jitter when the lower bit rate signal is recovered at the receiver end, the phase different between the two signals is determined more accurately. This effected with a counter (55, 56) whose count is applied to the phase comparator (7) to determine the digits after the decimal point for the phase difference.

Abstract: A single signal is formed from two plesiochronous signals. The first signal's data are written in parallel in groups of n bits each. Writing and reading are controlled by respective counters, whose counts are also provided to a subtractor. A control loop for bit rate justification is formed by the subtractor, a controller and the read counter. A track counter counts the stuffed bits modulo n, and stops the read counter for one clock period after each n stuffed bits. The mean value of the subtractor output and the count of the track counter are set off against each other, and their result is used for justification formation and a preparation signal for incrementing the track counter.

Abstract: A circuit arrangement for adapting the bit rates of two signals to each other and which comprises an elastic store (6). The useful data of a first frame-structured signal are written into this store (6) by means of a write address counter (7) and read out again by means of a read address counter (8). A phase comparator (16) is used for comparing the counts of these counters (7,8). In order to largely avoid jitter in the signal that has been read, a balancing counter (14) is provided which, on average, is stopped as often as the write address counter (7) is, but runs more smoothly than the write address counter. The means for controlling the operation of the balancing counter (14) comprise comparator circuits (12E, 12F, 12G) by means of which the operation of the frame counter (12) is monitored, an up/down counter (19) as well as various gates (11, 13, 17, 18).

Abstract: A circuit arrangement for converting the bit rate of a frame structured input signal to a predetermined nominal bit rate. The data bits of the input signal are written into an elastic store (6) at the bit rate of such signal by means of a write address counter (7), and subsequently read out again therefrom by means of a read address counter (8) at a rate within a tolerance range of the nominal bit rate. A phase comparator (16) determines the distance between the counts of such counters and produces a control error signal corresponding to such distance. In order to minimize jitter of the read out signal, the control error signal is supplied to a control circuit (18) which controls the clock produced by a clock generator (17) for the read address counter (8). The clock generator circuit includes a frequency controllable oscillator, the output of which serves as the read clock.

Abstract: A circuit arrangement for adapting the bit rates of two signals includes an elastic store into which the data of the first signal are written in parallel in groups of n bits and from which the data bits of the second signal are read out in parallel. A selection matrix for inserting justification bits in the second signal is connected to the output of the elastic store. Writing into the store is controlled by a write counter and read-out therefrom into the selection matrix is controlled by a read counter. A subtractor forms the difference between the counts. A justification decision circuit, which can be realized all or part in CMOS technology and is capable of bit rates of the order of 140 Mbits per second, is connected to the subtractor and the read counter so as to form a control loop for the elastic store.