Abstract: A compiler for a digital signal processor allows the designer to specify separately function, accuracy and throughput. The compiler employs a word structure having the signal attributes of bits, digits and subwords which all have a direct relationship to the size of the processor and throughput. From a budget of working bits and clock cycles implicit in the specification of accuracy and throughput the compiler is able to choose the optimal word structure for the application. The compiler can also propagate throughout an icon network, used for the specification of function, various estimation attributes such as word growth and quantisation noise, which allow the designer to observe the effect of design changes without recourse to simulation. A specific example of design employing a specified architecture and a specified computational grain is explained.

Abstract: A serial/parallel multiplier for the multiplication of a coefficient word with a data word of which the bits are broadcast n at a time where n is at least three. The structure comprises a plurality of pipes which where n is even each consists of a radix-4 encoder receiving two bits of the cluster and driving a partial product generator coupled to a respective carry-save array which forms the required two bits of the product by shifting and accumulation. For n equal to an odd number, the final sub-pipe consists of a radix-2 sub-pipe rather than a radix-4 sub-pipe and provides a single bit of the output, which consists of a cluster of n bits.