Abstract: Disclosed is a demand paging scheme for a shared memory processing system that uses paged virtual memory addressing and includes a plurality of address translation buffers (ATBs). Page frames of main memory that hold pages being considered for swapping from memory are sequestered and flags, one corresponding to each ATB in the system, are cleared. Each time an ATB is flushed, its associated flag is set. Setting of all the flags indicates that the address translation information of pages held by selected sequestered page frames does not appear in any ATB and that the selected pages may be swapped from main memory.

Abstract: This invention is an electronically steerable radar antenna which is on a cylinder section which is on the order of one wave length in circumference and in which the shape of the antenna elements on the cylinder section take the form of "O", "I" and "C" slots occupying about one-third the section circumference. Radar beams are steered by changing the phase and amplitude of the drive to the different elements of the antenna. The slots are formed as interruptions in an otherwise continuous, conductive ground plane and may be filled with dielectric if desired so that there is no surface discontinuity.

Abstract: A system (FIG. 1; FIGS. 18-19) performs addition or subtraction of packed, or binary-coded-decimal (BCD), values. Each BCD digit is stored in a nibble (500) of a register (400, 401). The least-significant bits (LSBs) (502) of corresponding nibbles of the registers are exclusive-ORed and results are stored in a third register (402) (FIG. 4 or 9). For addition, the registers' binary values are summed, six is added to each nibble of the sum using binary addition, and results are stored in one register (401) (FIG. 5). For subtraction, the registers' binary values are subtracted, and the results are stored in one register (401) (FIG. 10). The LSB of each nibble of the one register is compared with the corresponding exclusive-OR value from the third register (FIGS. 6 or 11).