Abstract: An addressing circuit designed for implementation within the device being addressed that uses less silicon space by selecting the desired address with shift register outputs. A fast shift register is coupled to a slow shift register by a combinatorial circuit having inputs from the fast shift register and the slow shift register to providing the selected address. A timing circuit is electrically coupled to each the fast shift register and the slow shift register. A mode select circuit that is operatively coupled to at least one of either the fast shift register or the slow shift register. The mode select circuit comprises a Boolean logic circuit that is operatively coupled to at least one of either the slow shift register or the fast shift register, the Boolean logic circuit having at least one logical input that determine a first portion of at least one of the shift registers to be used and a second portion of at least one of the shift registers to be discarded.

Abstract: A method and apparatus for generating timing signals within the sensor in an imaging system by making provisions internally within a sensor that allows the sensor to generate the timing signals which are then output to the system to control the image sensor timing This alleviates the system from the responsibility of counting pixels and lines. The sensor will give at predetermined times, outputs which have the same wave form as the normal video output but with a much higher amplitude than the maximum video output recognized by the image processing system. These output signals will identify the end of the line and likewise will identify the end of the frame (or field). The resulting sensor can maintain its own timing sequence accurately tracking the time for lines and frame readout.

Abstract: A system architecture is provided that includes an image sensor unit operable in a single channel mode and a dual channel mode. The image sensor unit includes an electronic image sensor comprising a row and column array of pixel elements, wherein the rows of the array having a line length of N pixels. First and second digital signal processing units for processing image data generated by the image sensor unit into color component image data are provided, wherein each of said first and second digital signal processing units has a line length processing capacity less than N pixels.

Abstract: A timing logic system which includes a generic television-standard timing generator selectably provides precisely timed horizontal and vertical control signals for controlling the operation of a high resolution charge coupled device (CCD) image sensor of the type having two line pixel registers in a high resolution mode of picture imaging. Alternatively, the timing logic system selectably provides precisely timed horizontal and vertical control signals, and a precisely timed display field control signal applied to a switch mechanism, for controlling the operation of the high resolution CCD image sensor in a television resolution mode of picture imaging in accordance with a television standard, for example, the NTSC standard. The timing logic system also provides sync and control signals to a television-standard display in the television mode of operation.

Abstract: A test system is provided for the dynamic testing at the same time of a plurality of packaged charge coupled device (CCD) image sensors in which the plurality of image sensors of the same sensor type can be tested under conditions including selectable signal levels of bias control signals and selected signal levels and pulse durations of clocked control signals appropriate to the type of CCD image sensor of the plurality of sensors under test. The test system provides selectably level-adjusted control signals, selector switch means for generating selectable clock signals having the level-adjusted signal levels, and a clock driver for amplifying the clocked control signals. The amplified control signals are directed to a common input terminal of an isolation network assembly, each of separate output terminals thereof connected to a corresponding input terminal of each one of the CCD image sensors to be tested.

Abstract: A high speed clock driver circuit for use with an area image sensor which has two horizontal shift registers is disclosed. Circuitry is provided which is responsive to the third level of one of the horizontal high speed clock driver signal and the vertical transfer signals for enabling the transfer, in parallel, of pixels from the first register into the second horizontal shift register.

Abstract: Apparatus and method for controlling a charge coupled device (CCD) image sensor provides in accordance with a television standard horizontal and vertical CCD control signals. The apparatus includes a frequency generator, a standard timing generator, a pixel clock generator, and a small number of additional timers and logic units which are driven by signals from the generators to generate the vertical and horizontal CCD control signals. The frequency of operation of the pixel clock generator is selectable in accordance with a number of pixels per horizontal line of the CCD image sensor. Various CCD image sensors having different numbers of pixels per horizontal line may be used. The method includes generating a plurality of precisely timed pulses referenced to television standard synchronizing and control signals, and logically combining these pulses and standard signals to generate the vertical and horizontal CCD control signals.

Abstract: Apparatus and method for controlling a high resolution charge coupled device (CCD) image sensor operate in accordance with a television standard to provide horizontal, vertical, and other CCD control signals to obtain a purely sequential high resolution mode of operation on the one hand. Alternatively, there is a modified mode of operation which provides interlaced even and odd groups of video signals to be viewed directly on a television viewfinder display. The apparatus includes a frequency generator, a standard timing generator, a pixel clock generator, and a small number of additional timers and logic units which are driven by signals from the generators to selectably generate the vertical, horizontal, and other CCD control signals for the alternate modes of operation.

Abstract: Reset, clamp, and sample pulses for a CCD sensor for electronic imaging applications are generated which have their leading edges delayed with respect to the leading edges of corresponding pixel clock pulses by substantially constant proportions of the pixel clock period independently of pixel frequency. To do this, a first auxiliary 50 percent duty cycle pulse train is generated having a frequency 4 times the pixel frequency. A divide by 4 counter receives the first auxiliary train and produces both the pixel clock itself and a second auxiliary 50 percent duty cycle pulse train having a frequency twice the pixel frequency. A 3 to 8 line decoder receives the pixel clock and both auxiliary trains to produce eight separate trains of pulses having the pixel frequency and a substantially 12.5 percent duty cycle.

Abstract: Apparatus and method for controlling a charge coupled device (CCD) image sensor provides, in accordance with a television standard, horizontal and vertical CCD control signals to obtain a purely sequential mode of operation on the one hand, and alternatively a modified mode of operation to permit image signals to be viewed directly on a standard viewfinder display. The apparatus includes a frequency generator, a standard timing generator, a pixel clock generator, and a small number of additional timers and logic units which are driven by signals from the generators to selectably generate the vertical and horizontal CCD control signals for the alternate modes of operation. The method includes generating a plurality of precisely timed pulses referenced to television standard synchronizing and control signals, and logically combining these pulses and standard signals to generate the vertical and horizontal CCD control signals.

Abstract: A power saving impedance transformation circuit for receiving a d-c biased signal comprises a junction transistor connected to operate as an emitter follower, means for connecting the base of the transistor to receive the signal, an operational amplifier having both inverting and non-inverting inputs, a first resistor connected between the emitter of the transistor and the operational amplifier inverting input, a second resistor equal to the first resistor in resistance and having one end connected to the operational amplifier inverting input, resistive means for connecting the other end of the second resistor to a first voltage source of a polarity which, in cooperation with the signal, forward biases the emitter-base junction of the transistor, the emitter-base junction of the transistor receiving its forward bias from the first voltage source exclusively through the first and second resistors and the resistive means, and means for connecting the collector of the transistor to a second voltage source of a p

Abstract: A time delayed digital circuit includes three circuits, each of which includes two inverters used in charging and discharging a capacitor to produce a precisely delayed output digital signal which can have wide variations.

Abstract: An apparatus for producing a visual image stored in a multi-output CCD image sensor for CCD image analysis which has a plurality of analog shift registers. Analog multiplexers are used to eliminate the need for a frame store.

Abstract: A plurality of linear image sensors of a contact array scanner are read out at relatively low sensor pixel rates using only a limited number of expensive digital components. For a contact array scanner having sensors with both forward and reverse readouts, outputs are selected and read together in parallel from successive pairs of forward sensor readouts. Individual outputs from each of the forward readout pairs are sequentially sampled and held and the samples from each of the forward readout pairs are digitized. Outputs are also selected and read together in parallel from successive pairs of reverse sensor readouts. Individual outputs from each of the reverse readout pairs are sequentially sampled and held and the samples from each of the reverse readout pairs are digitized.

Abstract: A time delayed digital circuit includes two inverters used in charging and disclosure a capacitor to produce a precisely delayed output digital signal.

Abstract: Clock driving circuitry for a high speed interline transfer CCD imager generates complementary voltage waveforms, each of which shifts from a respective first voltage level to a respective second voltage level once for every line in a frame to empty each of the imager's vertical shift registers in succession and to a respective third voltage level once each frame to charge all of the photodiodes of the imager. In generating one of the complementary waveforms, a positive third voltage level is superimposed upon the waveform through at least one isolation device and a separate switch is provided to discharge the waveform back to the second voltage level. In generating the other of the complementary waveforms, the waveform is switched from the second voltage level to a negative third voltage level and then switched back from the negative third voltage level to the second voltage level.

Abstract: A low cost system for efficiently doubling the data readout rate from a high resolution CCD video sensor having two line outputs includes a pair of analog to digital converters, a separate pair of first-in first-out line stores for each of the analog to digital converters, and a digital to analog converter. Successive lines from the video sensor are fed into alternate ones of the analog to digital converters in sequence at the normal pixel clock frequency used with other than high resolution sensors. The contents of successive lines in each of the analog to digital converters are written into alternate ones of its respective pair of line stores in sequence. The contents of successive lines from all of the line stores are fed into the digital to analog converter. Finally, analog data is read out of the digital to analog converter to the single analog input of a high resolution video monitor at twice the pixel clock frequency.

Abstract: A driver circuit, which is capable of operation in the 30 MHz frequency range and zero to +10 volts, is useful for driving charge coupled devices (CCDs). The driver circuit uses the parallel combination of an off the shelf bipolar integrated circuit capable of charging the CCD to about six volts and an off the shelf complementary field effect transistor transmission gate capable of charging the CCD to about +10 volts. The bipolar integrated circuit is capable of discharging the CCD from about +10 volts to zero volts (ground).

Abstract: The number of wires needed to supply a CCD sensor with the necessary control pulses is reduced by deriving such control pulses as the reset, sample and clamp pulses at the CCD sensor from an available source such as the horizontal clock signal. Although the horizontal clock signal may be significantly different in d-c reference level and amplitude from the needed control pulses, the control pulses are generated by translating the horizontal clock signal to a signal of the needed d-c reference level and amplitude and properly timing the generation of the necessary control pulses.

Abstract: A clock driver apparatus for remotely driving a CCD capacitive load includes a coaxial cable, a reactance load and a driver circuit having a resistor and diode connected in parallel at the output of the circuit to provide short circuit protection for the switching transistors of the driver circuit.