Patents by Inventor Ram Narayan
Ram Narayan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250158577Abstract: An example apparatus includes first interpolation circuitry; second interpolation circuitry; first frequency band envelope determination circuitry having an input coupled to the first interpolation circuitry, and having an output; second frequency band envelope determination circuitry having an input coupled to the second interpolation circuitry, and having an output; combiner circuitry having a first input coupled to the output of the first frequency band envelope determination circuitry, having a second input coupled to the output of the second frequency band envelope determination circuitry, and having an output; and signal monitor circuitry having an input coupled to the output of the combiner circuitry.Type: ApplicationFiled: January 31, 2024Publication date: May 15, 2025Inventors: Goutham Ramesh, Sarma Sundareswara Gunturi, Ram Narayan Krishna Nama Mony
-
Publication number: 20240364374Abstract: A circuit includes a capture subsystem and digital pre-distortion (DPD) circuitry. The capture subsystem is configured to capture a set of signal samples responsive to a capture enable signal. The DPD circuitry is configured to generate a signal statistics signal based on an input signal, generate a set of DPD coefficients based on the set of signal samples, and apply DPD correction to the input signal to produce an output signal based on the signal statistics signal and the set of DPD coefficients. The set of signal samples includes samples of the signal statistics signal.Type: ApplicationFiled: April 25, 2024Publication date: October 31, 2024Inventors: Sarma Sundareswara Gunturi, Nishant Kumar, Chandrasekhar Sriram, Jawaharlal Tangudu, Ram Narayan Krishna Nama Mony, Varun Padavu Devaraj ., Sashidharan Venkatraman, Pankaj Gaur
-
Patent number: 11948596Abstract: Embodiments may provide techniques that protect voice-controllable devices and systems such that the microphone can be shielded from attacking modulated laser beams. Embodiments may provide a physical device that may include two or more layers of integrated material that sits on top of the microphones of the voice-controllable devices and/or systems. The device may act as a physical barrier against the injected malicious laser beams while allowing sound waves reach the microphone for normal operation. For example, in an embodiment, an apparatus may comprise a first layer including at least one opening and a second layer including at least one opening, wherein the at least one opening in the first layer and the at least one opening in the second layer are arranged so as to block the passage of light, but to allow the passage of sound.Type: GrantFiled: March 11, 2021Date of Patent: April 2, 2024Assignee: Board of Regents, The University of Texas SystemInventors: Eugene Britto John, Ram Narayan Krishnan
-
Patent number: 11533068Abstract: A radio frequency transmitter includes an upconverter that outputs in-phase (I) and quadrature (Q) signals, a digital timing offset circuit, first and second digital-to-analog converters (DACs), an analog timing offset removal circuit, first and second pulse shapers, and an adder. The digital timing offset circuit introduces a time offset between the I and Q signals. The first and second DACs output analog I and Q signals, respectively, and have first and second clock signals, respectively. The first and second clock signals have the same frequency and are offset relative to each other by the time offset. The analog timing offset removal circuit removes the time offset between the analog I and Q signals. The first and second pulse shapers receive the analog I and Q signals, respectively, and output pulse-shaped I and Q signals. The adder receives the pulse-shaped I and Q signals and outputs an intermediate frequency signal.Type: GrantFiled: August 31, 2021Date of Patent: December 20, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rahul Sharma, Karthikeyan Gunasekaran, Sarma Sundareswara Gunturi, Ram Narayan Krishna Nama Mony, Jaiganesh Balakrishnan, Sandeep Kesrimal Oswal, Visvesvaraya Pentakota
-
Patent number: 11489517Abstract: A circuit includes a noise generator and a delay element. The output of the noise generator couples to the input of the delay element. The output of the delay element is coupled to a first input of a logic circuit, and the output of the noise generator is coupled to a second input of the logic circuit. The output of the logic circuit is coupled to a first control input of a waveform storage circuit. The waveform storage circuit is configured to produce a first digital waveform on its output responsive to a first logic state on the output of the logic circuit and to produce a second digital waveform on its output responsive to a second logic state on the output of the logic circuit. A sequencer has a sequencer output coupled to the second control input of the waveform storage circuit.Type: GrantFiled: December 22, 2021Date of Patent: November 1, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sriram Murali, Jaiganesh Balakrishnan, Ram Narayan Krishna Nama Mony, Pooja Sundar
-
Patent number: 11334941Abstract: Systems and methods are disclosed for determining one or more credit lines based on statistical approximations of credit line optimization models. By approximating the results of the optimization model, the disclosed embodiments may provide real-time account level credit line determinations based on fewer criteria than used in the optimization models. Other aspects of the disclosed embodiments are described herein.Type: GrantFiled: July 27, 2020Date of Patent: May 17, 2022Assignee: CAPITAL ONE SERVICES, LLCInventors: Antonello Loddo, Lu Su, Leonard Roseman, Ram Narayan
-
Publication number: 20220116030Abstract: A circuit includes a noise generator and a delay element. The output of the noise generator couples to the input of the delay element. The output of the delay element is coupled to a first input of a logic circuit, and the output of the noise generator is coupled to a second input of the logic circuit. The output of the logic circuit is coupled to a first control input of a waveform storage circuit. The waveform storage circuit is configured to produce a first digital waveform on its output responsive to a first logic state on the output of the logic circuit and to produce a second digital waveform on its output responsive to a second logic state on the output of the logic circuit. A sequencer has a sequencer output coupled to the second control input of the waveform storage circuit.Type: ApplicationFiled: December 22, 2021Publication date: April 14, 2022Inventors: Sriram MURALI, Jaiganesh BALAKRISHNAN, Ram Narayan KRISHNA NAMA MONY, Pooja SUNDAR
-
Patent number: 11239833Abstract: A circuit includes a noise generator and a delay element. The output of the noise generator couples to the input of the delay element. The output of the delay element is coupled to a first input of a logic circuit, and the output of the noise generator is coupled to a second input of the logic circuit. The output of the logic circuit is coupled to a first control input of a waveform storage circuit. The waveform storage circuit is configured to produce a first digital waveform on its output responsive to a first logic state on the output of the logic circuit and to produce a second digital waveform on its output responsive to a second logic state on the output of the logic circuit. A sequencer has a sequencer output coupled to the second control input of the waveform storage circuit.Type: GrantFiled: October 15, 2020Date of Patent: February 1, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sriram Murali, Jaiganesh Balakrishnan, Ram Narayan Krishna Nama Mony, Pooja Sundar
-
Publication number: 20210335383Abstract: Embodiments may provide techniques that protect voice-controllable devices and systems such that the microphone can be shielded from attacking modulated laser beams. Embodiments may provide a physical device that may include two or more layers of integrated material that sits on top of the microphones of the voice-controllable devices and/or systems. The device may act as a physical barrier against the injected malicious laser beams while allowing sound waves reach the microphone for normal operation. For example, in an embodiment, an apparatus may comprise a first layer including at least one opening and a second layer including at least one opening, wherein the at least one opening in the first layer and the at least one opening in the second layer are arranged so as to block the passage of light, but to allow the passage of sound.Type: ApplicationFiled: March 11, 2021Publication date: October 28, 2021Inventors: Eugene Britto John, Ram Narayan Krishnan
-
Patent number: 11063618Abstract: An IQ mismatch estimation circuit includes a raw channel estimation circuit, a reference channel estimation circuit, a digital predistortion (DPD) bin identification circuit, a channel estimate pruning circuit, and an IQ correction coefficient generation circuit. The raw channel estimation circuit generates raw channel estimates for a plurality of frequency bins of a baseband signal. The reference channel estimation circuit identifies a reference channel estimate based on the raw channel estimates. The DPD bin identification circuit identifies, based on the reference channel estimate, the frequency bins for which the raw channel estimates are based on a DPD expansion signal. The channel estimate pruning circuit generates pruned raw channel estimates by discarding the raw channel estimates of the frequency bins identified by the DPD bin identification circuit. The IQ correction coefficient generation circuit generates IQ mismatch correction coefficients based on the pruned raw channel estimates.Type: GrantFiled: July 30, 2020Date of Patent: July 13, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sashidharan Venkatraman, Jawaharlal Tangudu, Sarma Sundareswara Gunturi, Ram Narayan Krishna Nama Mony
-
Publication number: 20210119622Abstract: A circuit includes a noise generator and a delay element. The output of the noise generator couples to the input of the delay element. The output of the delay element is coupled to a first input of a logic circuit, and the output of the noise generator is coupled to a second input of the logic circuit. The output of the logic circuit is coupled to a first control input of a waveform storage circuit. The waveform storage circuit is configured to produce a first digital waveform on its output responsive to a first logic state on the output of the logic circuit and to produce a second digital waveform on its output responsive to a second logic state on the output of the logic circuit. A sequencer has a sequencer output coupled to the second control input of the waveform storage circuit.Type: ApplicationFiled: October 15, 2020Publication date: April 22, 2021Inventors: Sriram MURALI, Jaiganesh BALAKRISHNAN, Ram Narayan KRISHNA NAMA MONY, Pooja SUNDAR
-
Publication number: 20210083697Abstract: An IQ mismatch estimation circuit includes a raw channel estimation circuit, a reference channel estimation circuit, a digital predistortion (DPD) bin identification circuit, a channel estimate pruning circuit, and an IQ correction coefficient generation circuit. The raw channel estimation circuit generates raw channel estimates for a plurality of frequency bins of a baseband signal. The reference channel estimation circuit identifies a reference channel estimate based on the raw channel estimates. The DPD bin identification circuit identifies, based on the reference channel estimate, the frequency bins for which the raw channel estimates are based on a DPD expansion signal. The channel estimate pruning circuit generates pruned raw channel estimates by discarding the raw channel estimates of the frequency bins identified by the DPD bin identification circuit. The IQ correction coefficient generation circuit generates IQ mismatch correction coefficients based on the pruned raw channel estimates.Type: ApplicationFiled: July 30, 2020Publication date: March 18, 2021Inventors: Sashidharan Venkatraman, Jawaharlal Tangudu, Sarma Sundareswara Gunturi, Ram Narayan Krishna Nama Mony
-
Publication number: 20200357063Abstract: Systems and methods are disclosed for determining one or more credit lines based on statistical approximations of credit line optimization models. By approximating the results of the optimization model, the disclosed embodiments may provide real-time account level credit line determinations based on fewer criteria than used in the optimization models. Other aspects of the disclosed embodiments are described herein.Type: ApplicationFiled: July 27, 2020Publication date: November 12, 2020Applicant: Capital One Services, LLCInventors: Antonello Loddo, Lu Su, Leonard Roseman, Ram Narayan
-
Patent number: 10812294Abstract: A channel estimation method and system for IQ imbalance and local oscillator leakage correction, wherein an example of a channel estimation system comprising a calibrating signal generator configured to generate at least one pair of calibrating signals, a feedback IQ mismatch estimator configured to measure feedback IQ mismatch estimates based on the pair of calibrating signals, and a calibrating signal based channel estimator configured to generate a channel estimate based on the pair of calibrating signals and the feedback IQ mismatch estimates.Type: GrantFiled: November 15, 2019Date of Patent: October 20, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jawaharlal Tangudu, Sashidharan Venkatraman, Sarma Sundareswara Gunturi, Chandrasekhar Sriram, Sthanunathan Ramakrishnan, Ram Narayan Krishna Nama Mony
-
Patent number: 10762560Abstract: Systems and methods are disclosed for determining one or more credit lines based on statistical approximations of credit line optimization models. By approximating the results of the optimization model, the disclosed embodiments may provide real-time account level credit line determinations based on fewer criteria than used in the optimization models. Other aspects of the disclosed embodiments are described herein.Type: GrantFiled: February 23, 2018Date of Patent: September 1, 2020Assignee: Capital One Services, LLCInventors: Antonello Loddo, Lu Su, Leonard Roseman, Ram Narayan
-
Publication number: 20200169434Abstract: A channel estimation method and system for IQ imbalance and local oscillator leakage correction, wherein an example of a channel estimation system comprising a calibrating signal generator configured to generate at least one pair of calibrating signals, a feedback IQ mismatch estimator configured to measure feedback IQ mismatch estimates based on the pair of calibrating signals, and a calibrating signal based channel estimator configured to generate a channel estimate based on the pair of calibrating signals and the feedback IQ mismatch estimates.Type: ApplicationFiled: November 15, 2019Publication date: May 28, 2020Inventors: Jawaharlal TANGUDU, Sashidharan VENKATRAMAN, Sarma Sundareswara GUNTURI, Chandrasekhar SRIRAM, Sthanunathan RAMAKRISHNAN, Ram Narayan KRISHNA NAMA MONY
-
Patent number: 10643276Abstract: Systems and methods are disclosed for determining one or more credit lines based on statistical approximations of credit line optimization models. By approximating the results of the optimization model, the disclosed embodiments may provide real-time account level credit line determinations based on fewer criteria than used in the optimization models. Other aspects of the disclosed embodiments are described herein.Type: GrantFiled: March 10, 2014Date of Patent: May 5, 2020Assignee: Capital One Services, LLCInventors: Antonello Loddo, Lu Su, Leonard Roseman, Ram Narayan