Patents by Inventor Ram Sena Bojja

Ram Sena Bojja has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Pipelined row decoder topology for faster imager row decoding
    Patent number: 11223790
    Abstract: An imaging array includes a plurality of rows of pixel sensors. A timing pattern generator generates timing pattern control signals and provide the timing pattern control signals to every row in the array. Timing pattern control signals generated during a timing pattern period directed to operate the pixel sensors in a selected row. A latched row driver circuit includes an enable latch in each row of the array responsive to a row address enable signal provided prior to the timing pattern period to gate the timing pattern control signals to the pixel sensors in the selected row at the start of the timing pattern period. A row address generator circuit is coupled to the timing pattern generator and to the enable latches in each row of the array to generate the row address enable signal for each selected row prior to the timing pattern period.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: January 11, 2022
    Assignee: Foveon, Inc.
    Inventors: Ram Sena Bojja, Glenn Jay Keller, Alex Shiuh Wang
  • PIPELINED ROW DECODER TOPOLOGY FOR FASTER IMAGER ROW DECODING
    Publication number: 20210377484
    Abstract: An imaging array includes a plurality of rows of pixel sensors. A timing pattern generator generates timing pattern control signals and provide the timing pattern control signals to every row in the array. Timing pattern control signals generated during a timing pattern period directed to operate the pixel sensors in a selected row. A latched row driver circuit includes an enable latch in each row of the array responsive to a row address enable signal provided prior to the timing pattern period to gate the timing pattern control signals to the pixel sensors in the selected row at the start of the timing pattern period. A row address generator circuit is coupled to the timing pattern generator and to the enable latches in each row of the array to generate the row address enable signal for each selected row prior to the timing pattern period.
    Type: Application
    Filed: June 2, 2020
    Publication date: December 2, 2021
    Applicant: Foveon, Inc.
    Inventors: Ram Sena Bojja, Glenn Jay Keller, Alex Shiuh Wang