Abstract: A system for generating a true random number and implemented within an existing System on Chip (SoC) is provided herein. The system includes one or more sub circuitry synchronous modules configured to operate in a specified nominal clock rate, wherein each sub circuitry synchronous modules yields expected deterministic results when operating in its nominal clock rate; and a control module configured to clock the one or more sub circuitry synchronous modules each in a clock rate higher than its respective the nominal clock rate and beyond a specified value, to yield a non deterministic behavior of the one or more sub circuitry synchronous modules, resulting in one or more random signals, wherein the system is implemented within an existing system on chip (SOC).

Abstract: A system for generating a true random number and implemented within an existing System on Chip (SoC) is provided herein. The system includes one or more sub circuitry synchronous modules configured to operate in a specified nominal clock rate, wherein each sub circuitry synchronous modules yields expected deterministic results when operating in its nominal clock rate; and a control module configured to clock the one or more sub circuitry synchronous modules each in a clock rate higher than its respective the nominal clock rate and beyond a specified value, to yield a non deterministic behavior of the one or more sub circuitry synchronous modules, resulting in one or more random signals, wherein the system is implemented within an existing system on chip (SOC).