Abstract: Techniques are disclosed relating to reducing dynamic power consumption in integrated circuits. In some embodiments, simulation is performed at one or more stages of a circuit design to identify portions of the circuit with relatively high average clock switching activity, based on an amount of clock gating during the simulation by one or more clock gaters. In some embodiments, sequential circuit elements in the identified portions are specified as candidates for implementation using low-power sequential circuitry. Examples of low-power sequential circuitry include multibit flip flops and flip flops with low clock pin input capacitance. The disclosed techniques may allow automated design tools to significantly reduce dynamic power consumption while still meeting other design parameters such as timing constraints.

Abstract: An apparatus and method for transmitting/receiving a notification message in a Digital Video Broadcasting (DVB) system are provided, in which a terminal detects an Access Point (AP) from an Electronic Service Guide (ESG) bootstrapping session, queries the AP to request a notification message list or all or part of a notification message over a communication channel, and receives the notification message list or all or part of the notification message from the AP.

Abstract: A line receiver circuit having an input hysteresis characteristic which is compensated for both temperature changes and variations in supply voltage includes a receiver circuit portion, a bandgap circuit portion, a first voltage divider network, a second voltage divider network, and a feedback switching transistor. The receiver circuit portion is responsive to an input logic signal for generating an output signal. The bandgap circuit portion generates a constant reference voltage. The first and second voltage divider networks are operatively connected to the constant reference voltage. The switching transistor is responsive to the output signal for switching between the first voltage divider network generating a high threshold voltage when the input logic signal is in the low level state and the second voltage divider network generating a low threshold voltage when the input logic signal is in the high level state.