Patents by Inventor Ram Viswanath
Ram Viswanath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136244Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.Type: ApplicationFiled: December 22, 2023Publication date: April 25, 2024Applicant: Intel CorporationInventors: Debendra Mallik, Je-Young Chang, Ram Viswanath, Elah Bozorg-Grayeli, Ahmad Al Mohammad
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Patent number: 11935808Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.Type: GrantFiled: March 26, 2020Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Debendra Mallik, Je-Young Chang, Ram Viswanath, Elah Bozorg-Grayeli, Ahmad Al Mohammad
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Patent number: 11923267Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.Type: GrantFiled: March 26, 2020Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Debendra Mallik, Je-Young Chang, Ram Viswanath, Elah Bozorg-Grayeli, Ahmad Al Mohammad
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Publication number: 20240030142Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.Type: ApplicationFiled: October 2, 2023Publication date: January 25, 2024Applicant: Intel CorporationInventors: Sanka Ganesan, Ram Viswanath, Xavier Francois Brun, Tarek A. Ibrahim, Jason M. Gamba, Manish Dubey, Robert Alan May
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Patent number: 11817390Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.Type: GrantFiled: December 29, 2022Date of Patent: November 14, 2023Assignee: Intel CorporationInventors: Sanka Ganesan, Ram Viswanath, Xavier Francois Brun, Tarek A. Ibrahim, Jason M. Gamba, Manish Dubey, Robert Alan May
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Publication number: 20230290728Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.Type: ApplicationFiled: May 19, 2023Publication date: September 14, 2023Inventors: Andrew COLLINS, Bharat P. PENMECHA, Rajasekaran SWAMINATHAN, Ram VISWANATH
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Patent number: 11705398Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.Type: GrantFiled: January 26, 2022Date of Patent: July 18, 2023Assignee: Intel CorporationInventors: Andrew Collins, Bharat P. Penmecha, Rajasekaran Swaminathan, Ram Viswanath
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Publication number: 20230134770Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.Type: ApplicationFiled: December 29, 2022Publication date: May 4, 2023Applicant: Intel CorporationInventors: Sanka Ganesan, Ram Viswanath, Xavier Francois Brun, Tarek A. Ibrahim, Jason M. Gamba, Manish Dubey, Robert Alan May
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Patent number: 11640942Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.Type: GrantFiled: February 22, 2022Date of Patent: May 2, 2023Assignee: Intel CorporationInventors: Sanka Ganesan, Ram Viswanath, Xavier Francois Brun, Tarek A. Ibrahim, Jason M. Gamba, Manish Dubey, Robert Alan May
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Patent number: 11574851Abstract: An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled to a surface of the package substrate, a first material on the surface of the package substrate, the first material contacting one or more lateral sides of the integrated circuit device, the first material extending at least to a surface of the integrated circuit device opposite the package substrate, two or more separate fins over a surface of the integrated circuit device, the two or more fins comprising a second material having a different composition than the first material, and a third material having a different composition than the second material, the third material over the surface of the integrated circuit device and between the two or more fins. Other embodiments are also disclosed and claimed.Type: GrantFiled: February 27, 2019Date of Patent: February 7, 2023Assignee: Intel CorporationInventors: Aastha Uppal, Omkar Karhade, Ram Viswanath, Je-Young Chang, Weihua Tang, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Kumar Singh
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Patent number: 11545407Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.Type: GrantFiled: January 10, 2019Date of Patent: January 3, 2023Assignee: Intel CorporationInventors: Kumar Abhishek Singh, Omkar Karhade, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Aastha Uppal, Debendra Mallik, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Manish Dubey, Ravindranath Mahajan, Ram Viswanath, James C. Matayabas, Jr.
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Publication number: 20220181262Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.Type: ApplicationFiled: February 22, 2022Publication date: June 9, 2022Applicant: Intel CorporationInventors: Sanka Ganesan, Ram Viswanath, Xavier Francois Brun, Tarek A. Ibrahim, Jason M. Gamba, Manish Dubey, Robert Alan May
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Publication number: 20220148968Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.Type: ApplicationFiled: January 26, 2022Publication date: May 12, 2022Inventors: Andrew COLLINS, Bharat P. PENMECHA, Rajasekaran SWAMINATHAN, Ram VISWANATH
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Patent number: 11302643Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.Type: GrantFiled: March 25, 2020Date of Patent: April 12, 2022Inventors: Sanka Ganesan, Ram Viswanath, Xavier Francois Brun, Tarek A. Ibrahim, Jason M. Gamba, Manish Dubey, Robert Alan May
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Patent number: 11270942Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.Type: GrantFiled: April 3, 2020Date of Patent: March 8, 2022Assignee: Intel CorporationInventors: Andrew Collins, Bharat P. Penmecha, Rajasekaran Swaminathan, Ram Viswanath
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Publication number: 20210305121Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.Type: ApplicationFiled: March 26, 2020Publication date: September 30, 2021Applicant: Intel CorporationInventors: Debendra Mallik, Je-Young Chang, Ram Viswanath, Elah Bozorg-Grayeli, Ahmad Al Mohammad
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Publication number: 20210305162Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.Type: ApplicationFiled: March 25, 2020Publication date: September 30, 2021Applicant: Intel CorporationInventors: Sanka Ganesan, Ram Viswanath, Xavier Francois Brun, Tarek A. Ibrahim, Jason M. Gamba, Manish Dubey, Robert Alan May
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Publication number: 20210305119Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.Type: ApplicationFiled: March 26, 2020Publication date: September 30, 2021Applicant: Intel CorporationInventors: Debendra Mallik, Je-Young Chang, Ram Viswanath, Elah Bozorg-Grayeli, Ahmad Al Mohammad
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Publication number: 20210305120Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.Type: ApplicationFiled: March 26, 2020Publication date: September 30, 2021Applicant: Intel CorporationInventors: Debendra Mallik, Je-Young Chang, Ram Viswanath, Elah Bozorg-Grayeli, Ahmad Al Mohammad
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Publication number: 20200273772Abstract: An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled to a surface of the package substrate, a first material on the surface of the package substrate, the first material contacting one or more lateral sides of the integrated circuit device, the first material extending at least to a surface of the integrated circuit device opposite the package substrate, two or more separate fins over a surface of the integrated circuit device, the two or more fins comprising a second material having a different composition than the first material, and a third material having a different composition than the second material, the third material over the surface of the integrated circuit device and between the two or more fins. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: February 27, 2019Publication date: August 27, 2020Applicant: Intel CorporationInventors: Aastha Uppal, Omkar Karhade, Ram Viswanath, Je-Young Chang, Weihua Tang, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Kumar Singh