Patents by Inventor Rama GOPAL
Rama GOPAL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9569361Abstract: According to one general aspect, an apparatus may include a cache pre-fetcher, and a pre-fetch scheduler. The cache pre-fetcher may be configured to predict, based at least in part upon a virtual address, data to be retrieved from a memory system. The pre-fetch scheduler may be configured to convert the virtual address of the data to a physical address of the data, and request the data from one of a plurality of levels of the memory system. The memory system may include a plurality of levels, each level of the memory system configured to store data.Type: GrantFiled: July 7, 2014Date of Patent: February 14, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Arun Radhakrishnan, Kevin Lepak, Rama Gopal, Murali Chinnakonda, Karthik Sundaram, Brian Grayson
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Patent number: 9418018Abstract: A Fill Buffer (FB) based data forwarding scheme that stores a combination of Virtual Address (VA), TLB (Translation Look-aside Buffer) entry# or an indication of a location of a Page Table Entry (PTE) in the TLB, and a TLB page size information in the FB and uses these values to expedite FB forwarding. Load (Ld) operations send their non-translated VA for an early comparison against the VA entries in the FB, and are then further qualified with the TLB entry# to determine a “hit.” This hit determination is fast and enables FB forwarding at higher frequencies without waiting for a comparison of Physical Addresses (PA) to conclude in the FB. A safety mechanism may detect a false hit in the FB and generate a late load cancel indication to cancel the earlier-started FB forwarding by ignoring the data obtained as a result of the Ld execution. The Ld is then re-executed later and tries to complete successfully with the correct data.Type: GrantFiled: July 21, 2014Date of Patent: August 16, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Karthik Sundaram, Rama Gopal, Murali Chinnakonda
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Publication number: 20150199275Abstract: According to one general aspect, an apparatus may include a cache pre-fetcher, and a pre-fetch scheduler. The cache pre-fetcher may be configured to predict, based at least in part upon a virtual address, data to be retrieved from a memory system. The pre-fetch scheduler may be configured to convert the virtual address of the data to a physical address of the data, and request the data from one of a plurality of levels of the memory system. The memory system may include a plurality of levels, each level of the memory system configured to store data.Type: ApplicationFiled: July 7, 2014Publication date: July 16, 2015Inventors: Arun RADHAKRISHNAN, Kevin LEPAK, Rama GOPAL, Murali CHINNAKONDA, Karthik SUNDARAM, Brian GRAYSON
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Publication number: 20150186292Abstract: A Fill Buffer (FB) based data forwarding scheme that stores a combination of Virtual Address (VA), TLB (Translation Look-aside Buffer) entry# or an indication of a location of a Page Table Entry (PTE) in the TLB, and a TLB page size information in the FB and uses these values to expedite FB forwarding. Load (Ld) operations send their non-translated VA for an early comparison against the VA entries in the FB, and are then further qualified with the TLB entry# to determine a “hit.” This hit determination is fast and enables FB forwarding at higher frequencies without waiting for a comparison of Physical Addresses (PA) to conclude in the FB. A safety mechanism may detect a false hit in the FB and generate a late load cancel indication to cancel the earlier-started FB forwarding by ignoring the data obtained as a result of the Ld execution. The Ld is then re-executed later and tries to complete successfully with the correct data.Type: ApplicationFiled: July 21, 2014Publication date: July 2, 2015Inventors: Karthik SUNDARAM, Rama GOPAL, Murali CHINNAKONDA
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Patent number: 8933951Abstract: Techniques are described that track the lines and pixels in a frame buffer in the host system that are being modified and transmit these modified scan lines and modified pixel locations to the self refresh display instead of entire contents of the frame buffer. The graphics adapter informs the self refresh display of the modified scan lines or pixel information and then sends the pixel data over the communications channel to the display. Custom codes can be used to identify and transmit modified scan lines and pixels to the self refresh display logic.Type: GrantFiled: March 25, 2011Date of Patent: January 13, 2015Assignee: Intel CorporationInventors: Siddhartha Nath, Suresh Kumar, Rama Gopal Musunuri Satyanantha
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Patent number: 8842111Abstract: Techniques are described that can be used to adjust a refresh rate of a display device. For example, the refresh rate change can be triggered by a user application for a variety of circumstances such as a change in power source from AC to DC or display of 24 frames per second (fps) video. Contents of a primary buffer can be copied to a dummy buffer and a display engine can read video from the dummy buffer to provide video to a display. The clock rate of a clock used to read out pixels can be adjusted using software commands. Video is written to another buffer and during a vertical blanking interval, the display engine reads frames from the another buffer instead of the dummy buffer.Type: GrantFiled: September 20, 2010Date of Patent: September 23, 2014Assignee: Intel CorporationInventors: Srikanth Kambhatla, Sameer Kalathil Perazhi, Rama Gopal M. Satyanantha, Santosh K. Agrawal
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Publication number: 20120068993Abstract: Techniques are described that can be used to adjust a refresh rate of a display device. For example, the refresh rate change can be triggered by a user application for a variety of circumstances such as a change in power source from AC to DC or display of 24 frames per second (fps) video. Contents of a primary buffer can be copied to a secondary buffer and a display engine can read video from the secondary buffer to provide video to a display. The clock rate of a clock used to read out pixels can be adjusted using software commands. Video is written to a third buffer and during a vertical blanking interval the display engine reads frames from the third buffer instead of the second buffer.Type: ApplicationFiled: September 20, 2010Publication date: March 22, 2012Inventors: Srikanth Kambhatla, Sameer Kalathil Perazhi, Rama Gopal M. Satyanantha, Santosh K. Agrawal
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Publication number: 20110242116Abstract: Techniques are described that track the lines and pixels in a frame buffer in the host system that are being modified and transmit these modified scan lines and modified pixel locations to the self refresh display instead of entire contents of the frame buffer. The graphics adapter informs the self refresh display of the modified scan lines or pixel information and then sends the pixel data over the communications channel to the display. Custom codes can be used to identify and transmit modified scan lines and pixels to the self refresh display logic.Type: ApplicationFiled: March 25, 2011Publication date: October 6, 2011Inventors: Siddhartha Nath, Suresh Kumar, Rama Gopal Musunuri Satyanantha
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Patent number: 7127696Abstract: A mechanism for constructing Steiner trees using simultaneous blockage avoidance, delay optimization, and design density management are provided. An initial tiled timing-driven Steiner tree is obtained for an integrated circuit design. The Steiner tree is broken into 2-paths for which plates are generated designated the permissible area in which a Steiner point may migrate. Each 2-path is optimized by calculating a cost for each tile in the plate as a function of an environmental cost, a tile delay cost, and a trade-off value. A minimum cost tile is then selected as the point to which the Steiner point in the 2-path, if any, is to migrate. Once each 2-path is processed in this manner, routing is performed so as to minimize the cost at the source. This process may be iteratively repeated with new trade-off values until all of the nets have zero or positive slew.Type: GrantFiled: December 17, 2003Date of Patent: October 24, 2006Assignee: International Business Machines CorporationInventors: Charles Jay Alpert, Rama Gopal Gandham, Milos Hrkic, Stephen Thomas Quay
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Patent number: 7065730Abstract: A method, computer program product, and data processing system for porosity-aware buffered Steiner tree construction are disclosed. A preferred embodiment begins with a timing-driven Steiner tree generated without regard for porosity, then applies a plate-based adjustment guided by length-based buffer insertion. After performing localized blockage avoidance, the resulting tree is then passed to a buffer placement algorithm, such as van Ginneken's algorithm, to obtain a porosity-aware buffered Steiner tree.Type: GrantFiled: April 17, 2003Date of Patent: June 20, 2006Assignee: International Business Machines CorporationInventors: Charles Jay Alpert, Rama Gopal Gandham, Jiang Hu, Stephen Thomas Quay
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Patent number: 6958545Abstract: A system and method for correcting wiring congestion in a placed and partially or fully globally-routed VLSI chip design while avoiding adding new timing or electrical violations or other design constraints. Globally-congested areas are identified along with determining terminated and non-terminated wires in the congested areas. The process includes optimizing the identified congestion areas, incrementally rerouting affected nets, testing the resultant design legality and congestion metrics, and committing or reversing the optimizations and reroutings. The optimizations further includes the movement of logic cells and decomposition, recomposition or any other modification of logic cell structures (possibly combined with cell movement) to move terminated wires to less congested grid edges, rearrangement of commutative connections within or between cells, or addition of buffers to cause reroutes of feedthrough wires.Type: GrantFiled: January 12, 2004Date of Patent: October 25, 2005Assignee: International Business Machines CorporationInventors: Pooja M. Kotecha, Rama Gopal Gandham, Ruchir Puri, Louise H. Trevillyan, Adam P. Matheny
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Patent number: 6915496Abstract: An apparatus and method for incorporating driver sizing into buffer insertion such that the two optimization techniques are performed simultaneously are provided. The apparatus and method extends van Ginneken's algorithm to handle driver sizing by treating a source node as a “driver library.” With the apparatus and method, the circuit design is converted to a Steiner tree representation of the circuit design. Buffer insertion is performed on the Steiner tree using the van Ginneken algorithm to generate a first set of possible optimal solutions. For each solution in the first set, a driver of the same type as the original driver in the Steiner tree is selected from a driver library and virtually inserted into the solution. A delay penalty is retrieved for the selected driver, which is then used long with the new driver's characteristics to generate a second set of solutions based o the first set of solutions.Type: GrantFiled: September 26, 2002Date of Patent: July 5, 2005Assignee: International Business Machines CorporationInventors: Charles Jay Alpert, Chong-Nuen Chu, Rama Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen Thomas Quay
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Patent number: 6898774Abstract: A method, computer program product, and data processing system for inserting buffers into integrated circuit routing trees are disclosed. The present invention dynamically modifies a Steiner tree configuration as needed to derive a maximal slack solution that takes into account blockages such as those presented by IP blocks.Type: GrantFiled: December 18, 2002Date of Patent: May 24, 2005Assignee: International Business Machines CorporationInventors: Charles Jay Alpert, Rama Gopal Gandham, Jiang Hu, Stephen Thomas Quay
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Publication number: 20040216072Abstract: A method, computer program product, and data processing system for porosity-aware buffered Steiner tree construction are disclosed. A preferred embodiment begins with a timing-driven Steiner tree generated without regard for porosity, then applies a plate-based adjustment guided by length-based buffer insertion. After performing localized blockage avoidance, the resulting tree is then passed to a buffer placement algorithm, such as van Ginneken's algorithm, to obtain a porosity-aware buffered Steiner tree.Type: ApplicationFiled: April 17, 2003Publication date: October 28, 2004Applicant: International Business Machines CorporationInventors: Charles Jay Alpert, Rama Gopal Gandham, Jiang Hu, Stephen Thomas Quay
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Publication number: 20040123261Abstract: A method, computer program product, and data processing system for inserting buffers into integrated circuit routing trees are disclosed. The present invention dynamically modifies a Steiner tree configuration as needed to derive a maximal slack solution that takes into account blockages such as those presented by IP blocks.Type: ApplicationFiled: December 18, 2002Publication date: June 24, 2004Applicant: International Business Machines CorporationInventors: Charles Jay Alpert, Rama Gopal Gandham, Jiang Hu, Stephen Thomas Quay
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Publication number: 20040064793Abstract: An apparatus and method for incorporating driver sizing into buffer insertion such that the two optimization techniques are performed simultaneously are provided. In particular, the apparatus and method extends van Ginneken's algorithm to handle driver sizing by treating a source node as a “driver library”. With the apparatus and method, the circuit design is converted to a Steiner tree representation of the circuit design. Buffer insertion is performed on the Steiner tree using the van Ginneken algorithm to generate a first set of possible optimal solutions. For each solution in the first set, a driver of the same type as the original driver in the Steiner tree is selected from a driver library and virtually inserted into the solution. A delay penalty is retrieved for the selected driver. This delay penalty is then used along with the new driver's characteristics to generate a second set of solutions based on the first set of solutions.Type: ApplicationFiled: September 26, 2002Publication date: April 1, 2004Applicant: International Business Machines CorporationInventors: Charles Jay Alpert, Chong-Nuen Chu, Rama Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen Thomas Quay
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Patent number: 6591411Abstract: An apparatus and method for determining buffered Steiner trees for complex circuits is provided. The apparatus and method first clusters sinks with similar characteristics such as criticality, polarity and distance. The purpose of this step is to potentially isolate positive sinks from negative ones and non-critical sinks from critical ones. The present invention then constructs low-level Steiner trees over each of these clusters. Finally, a top-level timing driven Steiner tree is computed where each cluster is treated as a sink. The top-level tree is then merged with the low-level trees to yield a solution for the entire net.Type: GrantFiled: March 15, 2001Date of Patent: July 8, 2003Assignee: International Business Machines CorporationInventors: Charles Jay Alpert, Rama Gopal Gandham, Jiang Hu, Stephen Thomas Quay, Andrew James Sullivan
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Patent number: 6560752Abstract: An apparatus and method for buffer selection for use in buffer insertion is provided. An optimal buffer library generator module operates to reduce a general buffer library down to a optimal buffer library based on parameters that are input to the optimal buffer library generator module. Based on these parameters, the optimal buffer library generator module selects buffers from the general buffer library for inclusion in an optimal buffer library. In a preferred embodiment, the optimal buffer library is generated by generating a set of superior buffers and inverters and clustering the set of superior buffers. A single buffer is then selected from each cluster for inclusion in the optimal buffer library. The result is a smaller buffer library which will provide approximately the same performance during buffer insertion while reducing the amount of computing time and memory requirements.Type: GrantFiled: July 6, 2000Date of Patent: May 6, 2003Assignee: International Business Machines CorporationInventors: Charles Jay Alpert, Rama Gopal Gandham, Jose Luis Pontes Correia Neves, Stephen Thomas Quay
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Publication number: 20020133799Abstract: An apparatus and method for determining buffered Steiner trees for complex circuits is provided. The apparatus and method first clusters sinks with similar characteristics such as criticality, polarity and distance. The purpose of this step is to potentially isolate positive sinks from negative ones and non-critical sinks from critical ones. The present invention then constructs low-level Steiner trees over each of these clusters. Finally, a top-level timing driven Steiner tree is computed where each cluster is treated as a sink. The top-level tree is then merged with the low-level trees to yield a solution for the entire net.Type: ApplicationFiled: March 15, 2001Publication date: September 19, 2002Applicant: International Business Machines CorporationInventors: Charles Jay Alpert, Rama Gopal Gandham, Jiang Hu, Stephen Thomas Quay, Andrew James Sullivan
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Patent number: 6401234Abstract: A method and system for re-routing interconnects within an integrated circuit design having blockages and bays is disclosed. A net within the integrated circuit design is initially decomposed into multiple two-paths. The net includes interconnects previously routed by utilizing a Steiner tree routing algorithm. Next, a cost associated with each of the two-paths is calculated. A two-path having a a high cost is subsequently selected and re-routed with a lower cost two-path.Type: GrantFiled: December 17, 1999Date of Patent: June 4, 2002Assignee: International Business Machines CorporationInventors: Charles Jay Alpert, Rama Gopal Gandham, Jiang Hu, Jose Luis Neves, Stephen Thomas Quay