Patents by Inventor Rama Kishan MALLADI

Rama Kishan MALLADI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230309511
    Abstract: Techniques for autonomous animal movement are described. In some examples, animal tracking and movement software is used to provide input from a physical stimulus to direct movement of the animal coupled to an apparatus along a multi-turn route using physical output of the physical stimulus device based at least in part on a location of the animal with respect to a destination grazing area.
    Type: Application
    Filed: April 2, 2022
    Publication date: October 5, 2023
    Inventors: Elmoustapha OULD-AHMED-VALL, Rama Kishan MALLADI, Robert VAUGHN, Matthias HAHN, Sunny GOGAR
  • Patent number: 11256489
    Abstract: Systems, apparatuses and methods may provide for technology to identify in user code, a nested loop which would result in cache memory misses when executed. The technology further reverses an order of iterations of a first inner loop in the nested loop to obtain a modified nested loop. Reversing the order of iterations increases a number of times that cache memory hits occur when the modified nested loop is executed.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: February 22, 2022
    Assignee: Intel Corporation
    Inventors: Gautam Doshi, Rakesh Krishnaiyer, Rama Kishan Malladi
  • Patent number: 11194722
    Abstract: Apparatus and method for improved cache utilization and efficiency on a many-core processor. An apparatus comprising: a plurality of execution units to generate cache access requests responsive to executing instructions; a pending request queue to store pending cache access requests generated by the execution units; pending queue management circuitry to compare a current cache access request with entries in the pending request queue to determine whether the current cache access request can be merged with an entry in the pending request queue and, if so, to merge the current cache access request with the entry.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: December 7, 2021
    Assignee: INTEL CORPORATION
    Inventors: Bharath Narasimha Swamy, Joydeep Ray, Rama Kishan Malladi, James Valerio, Abhishek Appu
  • Publication number: 20200371763
    Abstract: Systems, apparatuses and methods may provide for technology to identify in user code, a nested loop which would result in cache memory misses when executed. The technology further reverses an order of iterations of a first inner loop in the nested loop to obtain a modified nested loop. Reversing the order of iterations increases a number of times that cache memory hits occur when the modified nested loop is executed.
    Type: Application
    Filed: September 22, 2017
    Publication date: November 26, 2020
    Inventors: Gautam Doshi, Rakesh Krishnaiyer, Rama Kishan Malladi
  • Publication number: 20190286563
    Abstract: Apparatus and method for improved cache utilization and efficiency on a many-core processor. An apparatus comprising: a plurality of execution units to generate cache access requests responsive to executing instructions; a pending request queue to store pending cache access requests generated by the execution units; pending queue management circuitry to compare a current cache access request with entries in the pending request queue to determine whether the current cache access request can be merged with an entry in the pending request queue and, if so, to merge the current cache access request with the entry.
    Type: Application
    Filed: March 15, 2018
    Publication date: September 19, 2019
    Inventors: Bharath Narasimha Swamy, Joydeep Ray, Rama Kishan Malladi, James Valerio, Abhishek Appu
  • Publication number: 20180253288
    Abstract: The present disclosure provides systems and methods for dynamically predicting and enhancing energy efficiency. Dynamically predicting and enhancing energy efficiency can include determining that the code path for the code executed at run time comprises a branch, selecting a path, corresponding to one of the plurality of versions of the code, from the branch based on the plurality of predictors, the plurality of metrics, and the plurality of versions of the code, and providing the code associated with the path to a processing unit for execution.
    Type: Application
    Filed: March 3, 2017
    Publication date: September 6, 2018
    Applicant: INTEL IP CORPORATION
    Inventors: Karthik RAMAN, William BROWN, Rama Kishan MALLADI, Andrey SEMIN