Patents by Inventor Rama N. Singh

Rama N. Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8880382
    Abstract: Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Saeed Bagheri, Fook-Luen Heng, Rajiv Vasant Joshi, Kafai Lai, David Osmond Melville, Saibal Mukhopadhyay, Alan E Rosenbluth, Rama N. Singh, Kehan Tian
  • Patent number: 8682634
    Abstract: Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Saeed Bagheri, Fook-Luen Heng, Rajiv Vasant Joshi, Kafai Lai, David Osmond Melville, Saibal Mukhopadhyay, Alan E Rosenbluth, Rama N. Singh, Kehan Tian
  • Patent number: 8510699
    Abstract: Techniques for generating variants of a circuit layout and evaluating quality of the variants are provided. In one aspect, a method for generating at least one variant layout for a cell design includes the following steps. At least a first basis layout and a second basis layout are obtained for the cell design, each having a plurality of shapes, each of the shapes being a polygon having a plurality of sides and vertices. One or more of the shapes in the first basis layout are linked with one or more of the shapes in the second basis layout that represent a common feature of the cell design resulting in a plurality of linked shapes. Starting with either the first basis layout or the second basis layout, a location of the vertices of each of the linked shapes are changed to produce the variant layout for the cell design.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: August 13, 2013
    Assignee: International Business Machines Corporation
    Inventors: Emrah Acar, Aditya Bansal, Rama N. Singh, Amith Singhee
  • Publication number: 20130185046
    Abstract: Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.
    Type: Application
    Filed: September 13, 2012
    Publication date: July 18, 2013
    Applicant: International Business Machines Corporation
    Inventors: Saeed Bagheri, Fook-Luen Heng, Rajiv Vasant Joshi, Kafai Lai, David Osmond Melville, Saibal Mukhopadhyay, Alan E. Rosenbluth, Rama N. Singh, Kehan Tian
  • Publication number: 20130185045
    Abstract: Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.
    Type: Application
    Filed: January 18, 2012
    Publication date: July 18, 2013
    Applicant: International Business Machines Corporation
    Inventors: Saeed BAGHERI, Fook-Luen HENG, Rajiv Vasant JOSHI, Kafai LAI, David Osmond MELVILLE, Saibal MUKHOPADHYAY, Alan E. ROSENBLUTH, Rama N. SINGH, Kehan TIAN
  • Patent number: 8473885
    Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: June 25, 2013
    Assignee: International Business Machines Corporation
    Inventors: John M. Cohn, James A. Culp, Ulrich A. Finkler, Fook-Luen Heng, Mark A. Lavin, Jin Fuw Lee, Lars W. Liebmann, Gregory A. Northrop, Nakgeuon Seong, Rama N. Singh, Leon Stok, Pieter J. Woeltgens
  • Patent number: 8219943
    Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: July 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: John M Cohn, James A. Culp, Ulrich A. Finkler, Fook-Luen Heng, Mark A. Lavin, Jin Fuw Lee, Lars W. Liebmann, Gregory A. Northrop, Nakgeuon Seong, Rama N. Singh, Leon Stok, Pieter J. Woeltgens
  • Publication number: 20120167029
    Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
    Type: Application
    Filed: March 7, 2012
    Publication date: June 28, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John M. Cohn, James A. Culp, Ulrich A. Finkler, Fook-Luen Heng, Mark A. Lavin, Jin Fuw Lee, Lars W. Liebmann, Gregory A. Northrop, Nakgeuon Seong, Rama N. Singh, Leon Stok, Pieter J. Woltgens
  • Patent number: 8122387
    Abstract: A method of physical design for integrated circuit (IC) chip fabrication, physical design system and program product therefor. A design shape is fragmented into segments for Optical Proximity Correction (OPC) and a harmonic mean of the segments is determined. Electrical intent is determined for the shape and a harmonic mean is determined for the segments. Segments may be moved based on a effect on the harmonic mean from moving the segments, measured using a harmonic mean cost function. Finally segmented shapes are passed to OPC.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: February 21, 2012
    Assignee: International Business Macines Corporation
    Inventors: Geng Han, Fook-Luen Heng, Jin Fuw Lee, Chao Yi Tien, legal representative, Rama N. Singh
  • Patent number: 7860701
    Abstract: A method for predicting functionality of an integrated circuit segment to be lithographically printed on a wafer. Initially there is provided a two-dimensional design of an integrated circuit, including an integrated circuit segment having critical width, and a two-dimensional printed image of the critical width integrated circuit segment is simulated. The method then includes determining a ratio of perimeters or areas of the designed critical width integrated circuit segment to the simulated printed critical width integrated circuit segment, and predicting functionality of the critical width integrated circuit segment after printing based on the ratio of perimeters or areas.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: December 28, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ioana Graur, Kafai Lai, Rama N. Singh
  • Publication number: 20100318956
    Abstract: A method of physical design for integrated circuit (IC) chip fabrication, physical design system and program product therefor. A design shape is fragmented into segments for Optical Proximity Correction (OPC) and a harmonic mean of the segments is determined. Electrical intent is determined for the shape and a harmonic mean is determined for the segments. Segments may be moved based on a effect on the harmonic mean from moving the segments, measured using a harmonic mean cost function. Finally segmented shapes are passed to OPC.
    Type: Application
    Filed: June 11, 2009
    Publication date: December 16, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Geng Han, Fook-Luen Heng, Jin Fuw Lee, Chao Yi Tien, Rama N. Singh
  • Patent number: 7831941
    Abstract: A methodology for obtaining improved prediction of CA resistance in electronic circuits and, particularly, an improved CA resistance model adapted to capture larger than anticipated “out of spec” regime. In one embodiment, a novel bucketization scheme is implemented that is codified to provide a circuit designer with considerably better design options for handling large CA variability as seen through the design manual. The tools developed for modeling the impact of CA variable resistance phenomena provide developers with a resistance model, such as conventionally known, modified with a new CA model Basis including a novel CA intrinsic resistance model, and, a novel CA layout bucketization model.
    Type: Grant
    Filed: January 2, 2008
    Date of Patent: November 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Fook-Luen Heng, Mark A. Lavin, Jin-Fuw Lee, Rama N. Singh, Roger Y. Tsai
  • Publication number: 20090204930
    Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
    Type: Application
    Filed: April 17, 2009
    Publication date: August 13, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John M. Cohn, James A. Culp, Ulrich A. Finkler, Fook-Luen Heng, Mark A. Lavin, Jin Fuw Lee, Lars W. Liebmann, Gregory A. Northrop, Nakgeuon Seong, Rama N. Singh, Leon Stok, Pieter J. Woltgens
  • Publication number: 20090171644
    Abstract: A methodology for obtaining improved prediction of CA resistance in electronic circuits and, particularly, an improved CA resistance model adapted to capture larger than anticipated “out of spec” regime. In one embodiment, a novel bucketization scheme is implemented that is codified to provide a circuit designer with considerably better design options for handling large CA variability as seen through the design manual. The tools developed for modeling the impact of CA variable resistance phenomena provide developers with a resistance model, such as conventionally known, modified with a new CA model Basis including a novel CA intrinsic resistance model, and, a novel CA layout bucketization model.
    Type: Application
    Filed: January 2, 2008
    Publication date: July 2, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dureseti Chidambarrao, Fook-Luen Heng, Mark A. Lavin, Jin-Fuw Lee, Rama N. Singh, Roger Y. Tsai
  • Patent number: 7536664
    Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: May 19, 2009
    Assignee: International Business Machines Corporation
    Inventors: John M. Cohn, James A. Culp, Ulrich A. Finkler, Fook-Luen Heng, Mark A. Lavin, Jin Fuw Lee, Lars W. Liebmann, Gregory A. Northrop, Nakgeuon Seong, Rama N. Singh, Leon Stok, Pieter J. Woltgens
  • Patent number: 7305334
    Abstract: A method for predicting functionality of an integrated circuit segment to be lithographically printed on a wafer. Initially there is provided a two-dimensional design of an integrated circuit, including an integrated circuit segment having critical width, and a two-dimensional printed image of the critical width integrated circuit segment is simulated. The method then includes determining a ratio of perimeters or areas of the designed critical width integrated circuit segment to the simulated printed critical width integrated circuit segment, and predicting functionality of the critical width integrated circuit segment after printing based on the ratio of perimeters or areas.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: December 4, 2007
    Assignee: International Business Machines Corporation
    Inventors: Ioana Graur, Kafai Lai, Rama N. Singh
  • Patent number: 7043712
    Abstract: A method of designing lithographic masks is provided where mask segments used in a model-based optical proximity correction (MBOPC) scheme are adaptively refined based on local image information, such as image intensity, gradient and curvature. The values of intensity, gradient and curvature are evaluated locally at predetermined evaluation points associated with each segment. An estimate of the image intensity between the local evaluation points is preferably obtained by curve fitting based only on values at the evaluation points. The decision to refine a segment is based on the deviation of the simulated image threshold contour from the target image threshold contour. The output mask layout will provide an image having improved fit to the target image, without a significant increase in computation cost.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: May 9, 2006
    Assignee: International Business Machines Corporation
    Inventors: Maharaj Mukherjee, Zachary Baum, Mark A. Lavin, Donald J. Samuels, Rama N. Singh
  • Patent number: 6648485
    Abstract: A light guide system has a light guide having a first end portion opposite a second end portion. The light guide provides a first surface and a second surface between the first and second end portions, and the second surface is inclined relative to the first surface. A light source is disposed along the first end portion on a first axis. A light redistribution device is disposed on an entrance of the light guide for receiving light from the light source and redistributing a portion of the light perpendicular to the first axis to provide a uniform light distribution from the first surface.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: November 18, 2003
    Assignee: International Business Machines Corporation
    Inventors: Evan G. Colgan, Fuad E. Doany, Akiko Nishikai, Rama N. Singh, Masaru Suzuki, Yoichi Taira
  • Patent number: 6600528
    Abstract: A display device provides a first optical device disposed in a light path for spatially separating angularly separated light into color components, and a pixel which receives each of the color components through a sub-pixel. Each sub-pixel controls transmitted light intensity therethrough. A black matrix is formed in operative relationship with the sub-pixels including apertures for receiving the color components. A microstructured layer is disposed in the light path and receives or transmits the color components from or to the apertures of the black matrix. The microstructured layer includes tilted and/or curved surfaces for redirecting laterally shifted color components shifted by the first optical device and may also diffuse light.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: July 29, 2003
    Assignee: International Business Machines Corporation
    Inventors: Evan G. Colgan, Rama N. Singh, Yoichi Taira, Robert L. Wisnieff, Fumiaki Yamada
  • Publication number: 20020075427
    Abstract: A display device provides a first optical device disposed in a light path for spatially separating angularly separated light into color components, and a pixel which receives each of the color components through a sub-pixel. Each sub-pixel controls transmitted light intensity therethrough. A black matrix is formed in operative relationship with the sub-pixels including apertures for receiving the color components. A microstructured layer is disposed in the light path and receives or transmits the color components from or to the apertures of the black matrix. The microstructured layer includes tilted and/or curved surfaces for redirecting laterally shifted color components shifted by the first optical device and may also diffuse light.
    Type: Application
    Filed: December 19, 2000
    Publication date: June 20, 2002
    Inventors: Evan G. Colgan, Rama N. Singh, Yoichi Taira, Robert L. Wisnieff, Fumiaki Yamada