Patents by Inventor Rama S.B. Harihara

Rama S.B. Harihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11971949
    Abstract: A graphics processing unit (GPU) and a method is disclosed that performs a convolution operation recast as a matrix multiplication operation. The GPU includes a register file, a processor and a state machine. The register file stores data of an input feature map and data of a filter weight kernel. The processor performs a convolution operation on data of the input feature map and data of the filter weight kernel as a matrix multiplication operation. The state machine facilitates performance of the convolution operation by unrolling the data of the input feature map and the data of the filter weight kernel in the register file. The state machine includes control registers that determine movement of data through the register file to perform the matrix multiplication operation on the data in the register file in an unrolled manner.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: April 30, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Christopher P. Frascati, Simon Waters, Rama S. B Harihara, David C. Tannenbaum
  • Publication number: 20220301095
    Abstract: A system and a method are disclosed improving forward progress of preempted workloads. A graphics pipeline processes tiles of a first low-priority job. A controller stops the first job by resetting the GPU and preempting the first job with a second job having a higher priority, determine whether the first job has been previously preempted one or more times, and adjust a batch-binning parameter reducing a likelihood that the first job will again be preempted in the current frame. In one embodiment, the controller is configured to stop the first job at a preemption boundary during a draw call or by resetting the GPU. A batch-binning parameter may include postponing sorting primitives into tiles during a binning process, increasing a number of tiles for backend rendering, reducing a quality of anti-aliasing, decreasing a shading rate quality, and/or decreasing input resolution and increasing upscaling of the first job.
    Type: Application
    Filed: June 24, 2021
    Publication date: September 22, 2022
    Inventors: Gabriel T. DAGANI, Christopher P. FRASCATI, FNU GURUPAD, David TANNENBAUM, Rama S.B. HARIHARA, Keshavan VARADARAJAN
  • Publication number: 20220197976
    Abstract: A graphics processing unit (GPU) and a method is disclosed that performs a convolution operation recast as a matrix multiplication operation. The GPU includes a register file, a processor and a state machine. The register file stores data of an input feature map and data of a filter weight kernel. The processor performs a convolution operation on data of the input feature map and data of the filter weight kernel as a matrix multiplication operation. The state machine facilitates performance of the convolution operation by unrolling the data of the input feature map and the data of the filter weight kernel in the register file. The state machine includes control registers that determine movement of data through the register file to perform the matrix multiplication operation on the data in the register file in an unrolled manner.
    Type: Application
    Filed: February 10, 2021
    Publication date: June 23, 2022
    Inventors: Christopher P. FRASCATI, Simon WATERS, Rama S.B HARIHARA, David C. TANNENBAUM
  • Patent number: 10796397
    Abstract: A mechanism is described for facilitating dynamic runtime transformation of graphics processing commands for improved graphics performance on computing devices. A method of embodiments, as described herein, includes detecting a command stream associated with an application, where the command stream includes dispatches. The method may further include evaluating processing parameters relating to each of the dispatches, where evaluating further includes associating a first plan with one or more of the dispatches to transform the command stream into a transformed command stream. The method may further include associating, based on the first plan, a second plan to the one or more of the dispatches, where the second plan represents the transformed command stream. The method may further include executing the second plan, where execution of the second plan includes processing the transformed command stream in lieu of the command stream.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: October 6, 2020
    Assignee: INTEL CORPORATION
    Inventors: James A. Valerio, Abhishek Venkatesh, Satyajit Sarangi, Michael Apodaca, Thomas F. Raoux, Hashem Hashemi, Rama S. B. Harihara
  • Publication number: 20160364828
    Abstract: A mechanism is described for facilitating dynamic runtime transformation of graphics processing commands for improved graphics performance on computing devices. A method of embodiments, as described herein, includes detecting a command stream associated with an application, where the command stream includes dispatches. The method may further include evaluating processing parameters relating to each of the dispatches, where evaluating further includes associating a first plan with one or more of the dispatches to transform the command stream into a transformed command stream. The method may further include associating, based on the first plan, a second plan to the one or more of the dispatches, where the second plan represents the transformed command stream. The method may further include executing the second plan, where execution of the second plan includes processing the transformed command stream in lieu of the command stream.
    Type: Application
    Filed: June 12, 2015
    Publication date: December 15, 2016
    Applicant: INTEL CORPORATION
    Inventors: James A. Valerio, Abhishek Venkatesh, Satyajit Sarangi, Michael Apodaca, Thomas F. Raoux, Hashem Hashemi, Rama S.B. Harihara