Abstract: A phase detection signal is generated with a phase detection logic pipeline and its associated tapped pipeline signal combinational logic circuit. The phase detection logic pipeline generates phase detection logic pipeline output signals from a first input clock signal and a second input clock signal. The first input clock signal is applied to a first flip-flop of a set of serially connected flip-flops to generate a pipeline signal. The pipeline signal is driven through the set of serially connected flip-flops by the second clock input signal. Logic pipeline output nodes connected between the serially connected flip-flops carry the phase detection logic pipeline output signals. The phase detection logic pipeline output signals are applied to the tapped pipeline signal combinational logic circuit, which logically combines the signals to generate the phase detection signal.

Abstract: A method for identifying false paths in a digital circuit. A list of paths corresponding to the digital circuit is either provided or generated. For each path, an AND gate is created. For each element in the path, the off-path signals of the monitor circuits corresponding to the elements of the path are coupled to the input of the AND gate. A plurality of different signals are input to the digital circuit in an attempt to generate a "1" at the output of the AND gate. A false timing path signal is generated for that path if the AND gate does not output a "1" within a pre-determined amount of time. This process is repeated for each path of the digital circuit to identify all false timing paths.

Abstract: Lists of candidate faults within an integrated circuit are generated, for the purpose of fault diagnosis, by performing a partial intersection of fault lists output from a full-scan test such as a JTAG test. The fault lists represent all candidate faults which may be responsible for producing a mismatched bit between an output test vector and an expected test vector provided by the full-scan test. The partial intersection is performed by first determining the number of occurrences of each candidate fault within all lists associated with each mismatched bit. Then, only faults which occur at least a pre-selected number of times are selected. In this manner, lists of candidate faulty gates are generated based on the relative degree of intersection between fault sets.

Abstract: A logic signal validity verifier for use in determining the validity of the logic states of a group of logic signals includes an inactive signal fault monitor for determining when all of the logic signals are in an inactive signal state and an active signal fault monitor for determining when more than one of the logic signals are in an active signal state. Where the logic signals are differential, the logic signal validity verifier further includes a differential signal fault monitor for determining when corresponding pairs of the differential logic signals are in the same active or inactive signal state.