Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a first n-type transistor having a first gate and a second n-type transistor having a second gate, and pre-decoder circuitry configured to provide a bias condition for the first gate and second gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises: a positive voltage for the first gate and a negative voltage for the second gate for a positive configuration for the memory cells, and zero volts for the first gate and the negative voltage for the second gate for a negative configuration for the memory cells.

Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.

Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a first n-type transistor having a first gate and a second n-type transistor having a second gate, and pre-decoder circuitry configured to provide a bias condition for the first gate and second gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises: a positive voltage for the first gate and a negative voltage for the second gate for a positive configuration for the memory cells, and zero volts for the first gate and the negative voltage for the second gate for a negative configuration for the memory cells.

Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.