Abstract: A method for using shared pins in a concurrent test execution environment is disclosed. The method relates to scheduling tests in concurrently executing test flows for automated test equipment (ATE) in a way so that resources can be shared between the test flows. The method comprises determining if any of a plurality of splits used by a first test contains at least one resource that is shared, wherein the first test and a second test are sequenced for execution in two separate concurrently executing test flows. The method further comprises determining if the first test should execute before the second test if the split is associated with resources required by both the second and first tests. Finally the method comprises reserving the split containing the at least one shared resource for access by the first test before beginning execution of the first test.

Abstract: A method for using shared pins in a concurrent test execution environment is disclosed. The method relates to scheduling tests in concurrently executing test flows for automated test equipment (ATE) in a way so that resources can be shared between the test flows. The method comprises determining if any of a plurality of splits used by a first test contains at least one resource that is shared, wherein the first test and a second test are sequenced for execution in two separate concurrently executing test flows. The method further comprises determining if the first test should execute before the second test if the split is associated with resources required by both the second and first tests. Finally the method comprises reserving the split containing the at least one shared resource for access by the first test before beginning execution of the first test.

Abstract: Test program development for a semiconductor test system, such as automated test equipment (ATE), using object-oriented constructs is described. The invention provides a method for describing test system resources, test system configuration, module configuration, test sequence, test plan, test condition, test pattern, and timing information in general-purpose object-oriented constructs, e.g., C++ objects and classes. In particular, the modularity of program development is suitable for developing test programs for an open architecture semiconductor test system.

Abstract: Test program development for a semiconductor test system, such as automated test equipment (ATE), using object-oriented constructs is described. The invention provides a method for describing test system resources, test system configuration, module configuration, test sequence, test plan, test condition, test pattern, and timing information in general-purpose object-oriented constructs, e.g., C++ objects and classes. In particular, the modularity of program development is suitable for developing test programs for an open architecture semiconductor test system.

Abstract: There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of

Abstract: There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of

Abstract: A method for developing a test program for a semiconductor test system is disclosed. The method includes describing a test plan file in a test program language (TPL), where the test plan file describes at least one test of the test program, describing a test class file in a system program language (SPL) and a corresponding pre-header file of the test class file in the TPL, where the test class file describes an implementation of the at least one test of the test program, and generating the test program using the test plan file, the test class file, and the pre-header file.

Abstract: A method for developing a test program for a semiconductor test system is disclosed. The method includes describing a test plan file in a test program language (TPL), where the test plan file describes at least one test of the test program, describing a test class file in a system program language (SPL) and a corresponding pre-header file of the test class file in the TPL, where the test class file describes an implementation of the at least one test of the test program, and generating the test program using the test plan file, the test class file, and the pre-header file.

Abstract: There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of

Abstract: Test program development for a semiconductor test system, such as automated test equipment (ATE), using object-oriented constructs is described. The invention provides a method for describing test system resources, test system configuration, module configuration, test sequence, test plan, test condition, test pattern, and timing information in general-purpose object-oriented constructs, e.g., C++ objects and classes. In particular, the modularity of program development is suitable for developing test programs for an open architecture semiconductor test system.