Abstract: Examples herein describe a method for memory address mapping. In one embodiment, the method includes selecting a bank group subset of bits from a plurality of bits that represent a memory address; selecting a bank address subset of bits from the plurality of bits; selecting a column subset of bits from the plurality of bits, wherein the column subset of bits is exclusive from the bank group subset of bits and the bank address subset of bits; and generating an optimal memory address mapping for converting system memory addresses into the plurality of local memory addresses for the memory banks using the bank group subset of bits, the bank address subset of bits, and the column subset of bits.

Abstract: Some examples of the present disclosure generally relate to integrated circuits that include hardware logic for detecting an edge of a signal. In some examples, an integrated circuit includes a traffic generator, a memory communication path, a comparator, and edge detection hardware logic. The traffic generator, comparator, and edge detection hardware logic are configurable based on a calibration stage. The traffic generator is operable to generate commands to memory via a memory communication path. The comparator is operable to compare data from the memory communication path with known data and to responsively output a comparison status. The data from the memory communication path is in response to the commands generated by the traffic generator. The edge detection hardware logic is operable to detect an edge of a signal based on the comparison status.