Abstract: In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.

Abstract: In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.

Abstract: In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.

Abstract: In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.

Abstract: In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.

Abstract: In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.

Abstract: Methods and apparatus relating to allocation of flow control credits for high performance devices are described. In some embodiments, controls and/or configuration structures may be provided for the OS (Operating System) or VMM (Virtual Machine Manager) to indicate possible processor affinity (e.g., of a device driver for a given PCIe device) to the platform components (in a platform dependent fashion, for example). Using this data, the platform components could configure the RC (Root Complex) ports and/or intermediate components (such as switches, bridges, etc.) to pre-allocate buffers for the links coupling the PCIe device to the RC ports or intermediate components. Other embodiments are also disclosed and claimed.

Abstract: Embodiments of system, method, and apparatus for virtualizing TPM accesses is described. In some embodiments, an apparatus including a CPU core to execute a software program, a manageability engine coupled to the CPU core, the manageability engine to receive a trusted platform module (TPM) command requested by the software program and to process the TPM command utilizing a manageability firmware by at least creating a TPM network packet, and a network interface coupled to the manageability engine to transmit the TPM network packet to a remote TPM that is external to the apparatus for processing is utilized as a part of this virtualization process.

Abstract: In one embodiment, the present invention includes a method for receiving a non-coherent atomic request from a device coupled to an agent via a non-coherent link, accessing a mapping table of the agent to convert the non-coherent atomic request into a coherent atomic request, and transmitting the coherent atomic request via a coherent link to a second agent coupled to the agent to cause the second agent to be a completer of the non-coherent atomic request. Other embodiments are described and claimed.

Abstract: An apparatus, method, system, and computer-readable medium are disclosed. In one embodiment the apparatus is a processor. The processor includes thread remapping logic that is capable of tracking hardware thread interrupt equivalence information for a first hardware thread and a second hardware thread. The processor also includes logic to receive an interrupt issued from a device, wherein the interrupt has an affinity tied to the first hardware thread. The processor also includes logic to redirect the interrupt to the second hardware thread when the hardware thread interrupt equivalence information validates the second hardware thread is capable of handling the interrupt.

Abstract: Embodiments of system, method, and apparatus for virtualizing TPM accesses is described. In some embodiments, an apparatus including a CPU core to execute a software program, a manageability engine coupled to the CPU core, the manageability engine to receive a trusted platform module (TPM) command requested by the software program and to process the TPM command utilizing a manageability firmware by at least creating a TPM network packet, and a network interface coupled to the manageability engine to transmit the TPM network packet to a remote TPM that is external to the apparatus for processing is utilized as a part of this virtualization process.

Abstract: In one embodiment, the present invention includes a method for receiving a non-coherent atomic request from a device coupled to an agent via a non-coherent link, accessing a mapping table of the agent to convert the non-coherent atomic request into a coherent atomic request, and transmitting the coherent atomic request via a coherent link to a second agent coupled to the agent to cause the second agent to be a completer of the non-coherent atomic request. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for receiving a non-coherent atomic request from a device coupled to an agent via a non-coherent link, accessing a mapping table of the agent to convert the non-coherent atomic request into a coherent atomic request, and transmitting the coherent atomic request via a coherent link to a second agent coupled to the agent to cause the second agent to be a completer of the non-coherent atomic request. Other embodiments are described and claimed.

Abstract: An apparatus, method, system, and computer-readable medium are disclosed. In one embodiment the apparatus is a processor. The processor includes thread remapping logic that is capable of tracking hardware thread interrupt equivalence information for a first hardware thread and a second hardware thread. The processor also includes logic to receive an interrupt issued from a device, wherein the interrupt has an affinity tied to the first hardware thread. The processor also includes logic to redirect the interrupt to the second hardware thread when the hardware thread interrupt equivalence information validates the second hardware thread is capable of handling the interrupt.

Abstract: An apparatus, method, system, and computer-readable medium are disclosed. In one embodiment the apparatus is a processor. The processor includes thread remapping logic that is capable of tracking hardware thread interrupt equivalence information for a first hardware thread and a second hardware thread. The processor also includes logic to receive an interrupt issued from a device, wherein the interrupt has an affinity tied to the first hardware thread. The processor also includes logic to redirect the interrupt to the second hardware thread when the hardware thread interrupt equivalence information validates the second hardware thread is capable of handling the interrupt.

Abstract: Methods and apparatus relating to allocation of flow control credits for high performance devices are described. In some embodiments, controls and/or configuration structures may be provided for the OS (Operating System) or VMM (Virtual Machine Manager) to indicate possible processor affinity (e.g., of a device driver for a given PCIe device) to the platform components (in a platform dependent fashion, for example). Using this data, the platform components could configure the RC (Root Complex) ports and/or intermediate components (such as switches, bridges, etc.) to pre-allocate buffers for the links coupling the PCIe device to the RC ports or intermediate components. Other embodiments are also disclosed and claimed.

Abstract: Embodiments of system, method, and apparatus for virtualizing TPM accesses is described. In some embodiments, an apparatus including a CPU core to execute a software program, a manageability engine coupled to the CPU core, the manageability engine to receive a trusted platform module (TPM) command requested by the software program and to process the TPM command utilizing a manageability firmware by at least creating a TPM network packet, and a network interface coupled to the manageability engine to transmit the TPM network packet to a remote TPM that is external to the apparatus for processing is utilized as a part of this virtualization process.

Abstract: In one embodiment, the present invention includes a method for receiving a non-coherent atomic request from a device coupled to an agent via a non-coherent link, accessing a mapping table of the agent to convert the non-coherent atomic request into a coherent atomic request, and transmitting the coherent atomic request via a coherent link to a second agent coupled to the agent to cause the second agent to be a completer of the non-coherent atomic request. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for receiving a non-coherent atomic request from a device coupled to an agent via a non-coherent link, accessing a mapping table of the agent to convert the non-coherent atomic request into a coherent atomic request, and transmitting the coherent atomic request via a coherent link to a second agent coupled to the agent to cause the second agent to be a completer of the non-coherent atomic request. Other embodiments are described and claimed.

Abstract: Methods and apparatus relating to atomic operations on multi-socket/multi-processor platforms are described. In one embodiment, a first agent (such as a processor core) is coupled to a second agent (such as an input/output device) via a link. A memory, coupled to the first agent, stores a device driver, corresponding to the second agent, and an operating system (OS) for the first agent. The OS detects an affinity mask that indicates which agents are to be quiesced for an atomic operation to be issued by the second agent. The agents identified by the affinity mask are then quiesced in response to receipt of the atomic operation from the second agent. Other embodiments are also disclosed and claimed.