Abstract: A system and method for automating and improving data extraction from a variety of document types, including both unstructured, structured, and nested content, is disclosed. The system and method incorporate an intelligent machine learning model that is designed to intelligently identify chunks of text, map the fields in the document, and extract multi-record values. The system is designed to operate with little to no human intervention, while offering significant gains in accuracy, data visualization, and efficiency. The architecture applies customized techniques including density-based adaptive text clustering, tabular data extraction based on hierarchical intelligent keyword searches, and natural language processing-based field value selection.

Abstract: The present disclosure provides one embodiment of a reflective electron-beam (e-beam) lithography system. The reflective e-beam lithography system includes an e-beam source to generate an e-beam; a digital pattern generator (DPG) having a plurality of pixels that are dynamically and individually controllable to reflect the e-beam; a substrate stage designed to secure a substrate and being operable to move the substrate; an e-beam lens module configured to project the e-beam from the DPG to the substrate; and an alignment gate configured between the e-beam source and the DPG, wherein the alignment gate is operable to modulate an intensity of the e-beam.

Abstract: A circuit for pulse width measurement comprises a charging circuit, a comparator and a determining circuit. The charging circuit is configured to charge a capacitive device in response to a periodic signal. The comparator is configured to compare a voltage across the capacitor with a reference voltage level. The determining circuit is configured to determine the number of pulses of the periodic signal in response to a signal from the comparator indicating that the voltage across the capacitor reaches the reference voltage level.

Abstract: A circuit for pulse width measurement comprises a charging circuit, a comparator and a determining circuit. The charging circuit is configured to charge a capacitive device in response to a periodic signal. The comparator is configured to compare a voltage across the capacitor with a reference voltage level. The determining circuit is configured to determine the number of pulses of the periodic signal in response to a signal from the comparator indicating that the voltage across the capacitor reaches the reference voltage level.

Abstract: The present disclosure provides one embodiment of a reflective electron-beam (e-beam) lithography system. The reflective e-beam lithography system includes an e-beam source to generate an e-beam; a digital pattern generator (DPG) having a plurality of pixels that are dynamically and individually controllable to reflect the e-beam; a substrate stage designed to secure a substrate and being operable to move the substrate; an e-beam lens module configured to project the e-beam from the DPG to the substrate; and an alignment gate configured between the e-beam source and the DPG, wherein the alignment gate is operable to modulate an intensity of the e-beam.

Abstract: A method of generating optimal packet workload for achieving a balance between maximizing cell throughput and fairness across multiple users in UMTS/HSPA Network is disclosed. The packet scheduler of the current invention enhances the performance of other schedulers, such as Proportionally Fair Scheduler in NodeB and RNC in UMTS/HSPA Networks by monitoring recent RAN bandwidth to each mobile device, and increasing buffer occupancy of high rate data-flows in the RAN devices. The scheduler uses the desired performance goals of maximum cell throughput and fairness at various network congestion levels, and controls egress burst rate while delivering packets to the RAN (Radio Access Network).

Abstract: A multi-operation mode application specific integrated circuit (ASIC) implemented in fully-depleted silicon-on-insulator (FDSOI) includes an ASIC implemented in FDSOI having a plurality of operating modes, plurality of power rails, and a power supply that provides voltages for the first and second rails corresponding to the plurality of operating modes. The power rails include at least one VDD rail, at least one Vss rail, a first rail for biasing a NGP region of PMOS transistor devices in the ASIC, and a second rail for biasing a PGP region of NMOS transistor devices in the ASIC.

Abstract: Memory devices and methods of operation are provided. A memory device includes first and second cross-coupled inverters and first and second access transistors coupled to an input node of the second inverter. The memory device also includes a control circuit for providing a first reference voltage at a first ground node of the first inverter and a second reference voltage at a second ground node of the second inverter. The first access transistor is configured to conduct current from a first bit line to the input node and to provide substantially no current conduction from the input node to the first bit line. The second access transistor is configured to conduct current from the input node to one of the first bit line and a second bit line and to provide substantially no current conduction from the input node to the one of first and second bit lines.

Abstract: Memory devices and methods of operation are provided. A memory device includes first and second cross-coupled inverters and first and second access transistors coupled to an input node of the second inverter. The memory device also includes a control circuit for providing a first reference voltage at a first ground node of the first inverter and a second reference voltage at a second ground node of the second inverter. The first access transistor is configured to conduct current from a first bit line to the input node and to provide substantially no current conduction from the input node to the first bit line. The second access transistor is configured to conduct current from the input node to one of the first bit line and a second bit line and to provide substantially no current conduction from the input node to the one of first and second bit lines.

Abstract: A method of generating optimal packet workload for achieving a balance between maximizing cell throughput and fairness across multiple users in UMTS/HSPA Network is disclosed. The packet scheduler of the current invention enhances the performance of other schedulers, such as Proportionally Fair Scheduler in NodeB and RNC in UMTS/HSPA Networks by monitoring recent RAN bandwidth to each mobile device, and increasing buffer occupancy of high rate data-flows in the RAN devices. The scheduler uses the desired performance goals of maximum cell throughput and fairness at various network congestion levels, and controls egress burst rate while delivering packets to the RAN (Radio Access Network).