Abstract: A hardware and software coordinated processor power state policy (e.g., policy for C-state) that delivers optimal power state selection by taking in to account the performance and/or responsiveness needs of thread expected to be scheduled on the core entering idle, to achieve improved IPC and performance for cores running user critical tasks. The scheme provides the ability to deliver responsiveness gains for important and/or user-critical threads running on a system-on-chip. A power management controller coupled to the plurality of processing cores, wherein the power management controller receives a hint from an operating system indicative of a bias towards a power state or performance state for at least one of the processing cores of the plurality of processing cores based on a priority of a thread in context switch.

Abstract: Techniques and mechanisms to dynamically prioritize communication of a data flow based on an indication of a user's interest in a particular task. In an embodiment, data flows correspond to different respective tasks that are executed with a host operating system. An output of a human interface device indicates whether, at a particular time, a user of a computer device is interested in one particular task over another task. Where greater user interest in a first task is indicated, a first packet type corresponding to the first task is assigned a relatively high priority, as compared to a second packet type which corresponds to a second task. Based on the priority, a resource of the network interface is selectively made available (or prevented from being made available) for the communication of a given packet. In another embodiment, the resource includes a queue of the network interface.

Abstract: Systems, apparatuses and methods may provide for technology that identifies a thread and selects a core from a plurality of processor cores in response to the selected core being available while satisfying a least used condition with respect to the plurality of processor cores. The technology may also schedule the thread to be executed on the selected core.

Abstract: Systems, apparatuses and methods may provide for technology that identifies a thread and selects a core from a plurality of processor cores in response to the selected core being available while satisfying a least used condition with respect to the plurality of processor cores. The technology may also schedule the thread to be executed on the selected core.