Patents by Inventor Ramana V. Katragadda

Ramana V. Katragadda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7577799
    Abstract: The present invention provides a system and method for implementation and use of a shared memory. The shared memory may be accessed both independently and asynchronously by one or more processes at corresponding nodes, allowing data to be streamed to multiple processes and nodes without regard to synchronization of the plurality of processes. The various nodes may be adaptive computing nodes, kernel or controller nodes, or one or more host processor nodes. The present invention maintains memory integrity, not allowing memory overruns, underruns, or deadlocks. The present invention also provides for “push back” after a memory read, for applications in which it is desirable to “unread” some elements previously read from the memory.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: August 18, 2009
    Assignee: NVIDIA Corporation
    Inventors: Ric Howard, Ramana V. Katragadda
  • Patent number: 7360216
    Abstract: A method of selecting tasks for execution on a processing node is provided. A plurality of indications of execution times corresponding to a first plurality of tasks is received. Also, a plurality of indications of maximum allowable latencies corresponding to the first plurality of tasks is received. At least a subset of the first plurality of tasks is selected for execution on the processing node based on the plurality of indications of execution times and the plurality of indications of maximum allowable latencies.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: April 15, 2008
    Assignee: NVIDIA Corporation
    Inventors: Paul L. Spoltore, Ramana V. Katragadda
  • Patent number: 7174432
    Abstract: The present invention provides a system and method for implementation and use of a shared memory. The shared memory may be accessed both independently and asynchronously by one or more processes at corresponding nodes, allowing data to be streamed to multiple processes and nodes without regard to synchronization of the plurality of processes. The various nodes may be adaptive computing nodes, kernel or controller nodes, or one or more host processor nodes. The present invention maintains memory integrity, not allowing memory overruns, underruns, or deadlocks. The present invention also provides for “push back” after a memory read, for applications in which it is desirable to “unread” some elements previously read from the memory.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: February 6, 2007
    Assignee: NVIDIA Corporation
    Inventors: Ric Howard, Ramana V. Katragadda
  • Publication number: 20040015971
    Abstract: A method of selecting tasks for execution on a processing node is provided. A plurality of indications of execution times corresponding to a first plurality of tasks is received. Also, a plurality of indications of maximum allowable latencies corresponding to the first plurality of tasks is received. At least a subset of the first plurality of tasks is selected for execution on the processing node based on the plurality of indications of execution times and the plurality of indications of maximum allowable latencies.
    Type: Application
    Filed: July 3, 2002
    Publication date: January 22, 2004
    Applicant: Quicksilver Technology, Inc.
    Inventors: Paul L. Spoltore, Ramana V. Katragadda