Patents by Inventor Ramana V. Rachakonda
Ramana V. Rachakonda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240119886Abstract: An electronic device may include a display panel. When content of an image frame is expected to consume relatively higher amounts of power, a controller of the electronic device may operate a switch to change a power supply of the display panel to be a power management integrated circuit of the electronic device. However, when content of an image frame is expected to consume relatively less amounts of power, the controller may operate the switch to change the power supply of the display panel to be a power supply of an electronic display, such as a power supply used to power driver circuitry of the electronic display.Type: ApplicationFiled: December 19, 2023Publication date: April 11, 2024Inventors: Peter F Holland, Christopher P Tann, Ramana V Rachakonda
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Publication number: 20240096263Abstract: A device may include image processing circuitry that generates image data corresponding to an image to be displayed during a first image frame and a second image frame. However, the image data is not regenerated for the second image frame. The device may also include an electronic display having a frame buffer that receives and stores the image data from the image processing circuitry. The electronic display may also include a display panel that displays the image during the first image frame based on a first read of the image data from the frame buffer in response to a first emission sync signal and displays the image during the second image frame based on a second read of the image data from the frame buffer in response to a second emission sync signal.Type: ApplicationFiled: July 17, 2023Publication date: March 21, 2024Inventors: Denis M. Darmon, Christopher P. Tann, Hopil Bae, Yanghyo Kim, Ramana V. Rachakonda, Xiaofeng Wang, Robert D. Zucker
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Publication number: 20240094797Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.Type: ApplicationFiled: September 28, 2023Publication date: March 21, 2024Inventors: Ramana V. Rachakonda, Rohit K. Gupta, Brad W. Simeral, Peter F. Holland
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Patent number: 11893925Abstract: An electronic device may include a display panel. When content of an image frame is expected to consume relatively higher amounts of power, a controller of the electronic device may operate a switch to change a power supply of the display panel to be a power management integrated circuit of the electronic device. However, when content of an image frame is expected to consume relatively less amounts of power, the controller may operate the switch to change the power supply of the display panel to be a power supply of an electronic display, such as a power supply used to power driver circuitry of the electronic display.Type: GrantFiled: May 4, 2022Date of Patent: February 6, 2024Assignee: Apple Inc.Inventors: Peter F Holland, Christopher P Tann, Ramana V Rachakonda
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Publication number: 20230394276Abstract: Embodiments relate to streaming convolution operations in a neural processor circuit that includes a neural engine circuit and a neural task manager. The neural task manager obtains multiple task descriptors and multiple subtask descriptors. Each task descriptor identifies a respective set of the convolution operations of a respective layer of a set of layers. Each subtask descriptor identifies a corresponding task descriptor and a subset of the convolution operations on a portion of a layer of the set of layers identified by the corresponding task descriptor. The neural processor circuit configures the neural engine circuit for execution of the subset of the convolution operations using the corresponding task descriptor. The neural engine circuit performs the subset of the convolution operations to generate output data that correspond to input data of another subset of the convolution operations identified by another subtask descriptor from the list of subtask descriptors.Type: ApplicationFiled: June 6, 2022Publication date: December 7, 2023Inventors: Sayyed Karen Khatamifard, Chenfan Sun, Alon Yaakov, Husam Khashiboun, Jeffrey D. Marker, Saman Naderiparizi, Ramana V. Rachakonda, Rohit K. Gupta
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Patent number: 11822416Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.Type: GrantFiled: September 23, 2022Date of Patent: November 21, 2023Assignee: Apple Inc.Inventors: Ramana V. Rachakonda, Rohit K. Gupta, Brad W. Simeral, Peter F. Holland
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Publication number: 20230368008Abstract: Embodiments relate to streaming operations in a neural processor circuit that includes a neural engine circuit and a data processor circuit. The neural engine circuit performs first operations on a first input tensor of a first layer to generate a first output tensor, and second operations on a second input tensor of a second layer at a higher hierarchy than the first layer, the second input tensor corresponding to the first output tensor. The data processor circuit stores a portion of the first input tensor for access by the neural engine circuit to perform a subset of the first operations and generate a portion of the first output tensor. The data processor circuit stores the portion of the first output tensor for access by the neural engine circuit as a portion of the second input tensor to perform a subset of the second operations.Type: ApplicationFiled: May 16, 2022Publication date: November 16, 2023Inventors: Sayyed Karen Khatamifard, Alexander J. Kirchhoff, Rohit K. Gupta, Jeffrey D. Marker, Thomas G. Anderl, Saman Naderiparizi, Chenfan Sun, Alon Yaakov, Husam Khashiboun, Ramana V. Rachakonda
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Patent number: 11614791Abstract: An electronic device may include a display panel. When content of an image frame is expected to consume relatively higher amounts of power, a controller of the electronic device may operate a switch to change a power supply of the display panel to be a power management integrated circuit of the electronic device. However, when content of an image frame is expected to consume relatively less amounts of power, the controller may operate the switch to change the power supply of the display panel to be a power supply of an electronic display, such as a power supply used to power driver circuitry of the electronic display.Type: GrantFiled: December 3, 2020Date of Patent: March 28, 2023Assignee: Apple Inc.Inventors: Ramana V. Rachakonda, Peter F. Holland, Rohit K. Gupta, Brad W. Simeral
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Publication number: 20230084199Abstract: An electronic device may include a display panel. When content of an image frame is expected to consume relatively higher amounts of power, a controller of the electronic device may operate a switch to change a power supply of the display panel to be a power management integrated circuit of the electronic device. However, when content of an image frame is expected to consume relatively less amounts of power, the controller may operate the switch to change the power supply of the display panel to be a power supply of an electronic display, such as a power supply used to power driver circuitry of the electronic display.Type: ApplicationFiled: May 4, 2022Publication date: March 16, 2023Inventors: Peter F Holland, Christopher P Tann, Ramana V Rachakonda
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Publication number: 20230082091Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.Type: ApplicationFiled: September 23, 2022Publication date: March 16, 2023Inventors: Ramana V. Rachakonda, Rohit K. Gupta, Brad W. Simeral, Peter F. Holland
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Publication number: 20230014545Abstract: An electronic device may include a display panel. When content of an image frame is expected to consume relatively higher amounts of power, a controller of the electronic device may operate a switch to change a power supply of the display panel to be a power management integrated circuit of the electronic device. However, when content of an image frame is expected to consume relatively less amounts of power, the controller may operate the switch to change the power supply of the display panel to be a power supply of an electronic display, such as a power supply used to power driver circuitry of the electronic display.Type: ApplicationFiled: September 21, 2022Publication date: January 19, 2023Inventors: Ramana V. Rachakonda, Peter F. Holland, Rohit K. Gupta, Brad W. Simeral
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Patent number: 11500448Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.Type: GrantFiled: September 9, 2020Date of Patent: November 15, 2022Assignee: Apple Inc.Inventors: Ramana V. Rachakonda, Rohit K. Gupta, Brad W. Simeral, Peter F. Holland
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Publication number: 20220083122Abstract: An electronic device may include a display panel. When content of an image frame is expected to consume relatively higher amounts of power, a controller of the electronic device may operate a switch to change a power supply of the display panel to be a power management integrated circuit of the electronic device. However, when content of an image frame is expected to consume relatively less amounts of power, the controller may operate the switch to change the power supply of the display panel to be a power supply of an electronic display, such as a power supply used to power driver circuitry of the electronic display.Type: ApplicationFiled: December 3, 2020Publication date: March 17, 2022Inventors: Ramana V. Rachakonda, Peter F. Holland, Rohit K. Gupta, Brad W. Simeral
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Publication number: 20220075440Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.Type: ApplicationFiled: September 9, 2020Publication date: March 10, 2022Inventors: Ramana V. Rachakonda, Rohit K. Gupta, Brad W. Simeral, Peter F. Holland
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Patent number: 6976047Abstract: A method and apparatus are used to generate FFT data addresses for a butterfly stage based upon a computation stage value. The method includes setting a selected bit of a binary word at a logical value, performing an addition operation by adding a logical “1” to the binary word, and skipping a carry bit as selected by a one-hot decoded stage value during the addition operation. The apparatus includes consecutive adders configured to store a binary value and perform an addition operation on the binary value, multiplexers configured to select either the carry out output of the current consecutive half adder or the carry out output of the previous consecutive half adder as the carry in input of a next consecutive adder, and sets of logic gates that provide one bit of the data address.Type: GrantFiled: March 28, 2002Date of Patent: December 13, 2005Assignee: Lattice Semiconductor CorporationInventor: Ramana V. Rachakonda