Patents by Inventor Ramanan Chebiam

Ramanan Chebiam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210098387
    Abstract: Composite integrated circuit (IC) device structures that include two components coupled through a hybrid bonded composite interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over substantially planar dielectric and metallization interfaces. Composite interconnect metallization features formed at a bond interface may be doped with a metal or chalcogenide dopant. The dopant may migrate to a periphery of the composite interconnect structure and form a barrier material that will then limit outdiffusion of a metal, such as copper, into adjacent dielectric material.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Applicant: Intel Corporation
    Inventors: Carl Naylor, Mauro Kobrinsky, Richard Vreeland, Ramanan Chebiam, William Brezinski, Brennen Mueller, Jeffery Bielefeld
  • Publication number: 20210098360
    Abstract: An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Applicant: Intel Corporation
    Inventors: Manish Chandhok, Ramanan Chebiam, Brennen Mueller, Colin Carver, Jeffery Bielefeld, Nafees Kabir, Richard Vreeland, William Brezinski
  • Patent number: 9391019
    Abstract: Interconnect structures including a selective via post disposed on a top surface of a lower level interconnect feature, and fabrication techniques to selectively form such a post. Following embodiments herein, a minimum interconnect line spacing may be maintained independent of registration error in a via opening. In embodiments, a selective via post has a bottom lateral dimension smaller than that of a via opening within which the post is disposed. Formation of a conductive via post may be preferential to a top surface of the lower interconnect feature exposed by the via opening. A subsequently deposited dielectric material backfills portions of a via opening extending beyond the interconnect feature where no conductive via post was formed. An upper level interconnect feature is landed on the selective via post to electrically interconnect with the lower level feature.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: July 12, 2016
    Assignee: Intel Corporation
    Inventors: Mauro Kobrinsky, Tatyana Andryushchenko, Ramanan Chebiam, Hui Jae Yoo
  • Publication number: 20150270211
    Abstract: Interconnect structures including a selective via post disposed on a top surface of a lower level interconnect feature, and fabrication techniques to selectively form such a post. Following embodiments herein, a minimum interconnect line spacing may be maintained independent of registration error in a via opening. In embodiments, a selective via post has a bottom lateral dimension smaller than that of a via opening within which the post is disposed. Formation of a conductive via post may be preferential to a top surface of the lower interconnect feature exposed by the via opening. A subsequently deposited dielectric material backfills portions of a via opening extending beyond the interconnect feature where no conductive via post was formed. An upper level interconnect feature is landed on the selective via post to electrically interconnect with the lower level feature.
    Type: Application
    Filed: March 20, 2014
    Publication date: September 24, 2015
    Inventors: Mauro Kobrinsky, Tatyania Andryushchenko, Ramanan Chebiam, Hui Jae Yoo
  • Publication number: 20090315185
    Abstract: A method for forming dual salicide contacts includes depositing a low or mid-gap work function metal selectively on an NMOS source/drain (S/D) region of a semiconductor device via electroless deposition; depositing a high work function metal selectively over the low work function metal and a PMOS source/drain (S/D) region of a semiconductor device via electroless deposition; annealing the semiconductor device to form a silicide of the low work function metal over the NMOS source/drain (S/D) region and a silicide of the high work function metal over the PMOS source/drain (S/D) region; and performing a SALICIDE etch to remove the unreacted metals from all regions of the substrate.
    Type: Application
    Filed: June 20, 2008
    Publication date: December 24, 2009
    Inventors: Boyan Boyanov, Ramanan Chebiam
  • Publication number: 20090166867
    Abstract: Cu interconnect structures using a bottomless liner to reduce the copper interfacial electron scattering and lower the electrical resistance are described in this application. The interconnect structures comprise a nucleation layer and a liner layer that may be formed by an oxide or nitride. The bottom portion of the liner layer is removed to expose the nucleation layer. Since the liner is bottomless, the nucleation layer is exposed during Cu deposition and serves to catalyze copper nucleation and enable selective growth of copper near the bottom (where the nucleation layer is exposed), rather than near the liner sidewalls. Thus, copper may be selectively grown with a bottom-up fill behavior than can reduce or eliminate formation of voids. Other embodiments are described.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Inventors: Harsono Simka, Sadasivan Shankar, Michael Haverty, Ramanan Chebiam, Florian Gstrein
  • Patent number: 7470617
    Abstract: In one embodiment, the present invention includes a method for depositing a barrier layer on a substrate having a trench, depositing a liner layer on the barrier layer that includes a surface oxide, electrolessly depositing a copper seed layer on the liner layer, where the surface oxide is reduced in-situ in an electroless bath, depositing a bulk metal layer on the copper seed layer. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: December 30, 2008
    Assignee: Intel Corporation
    Inventors: Ramanan Chebiam, Chin-Chang Cheng, Damian Whitney, Harsono Simka
  • Publication number: 20080213994
    Abstract: In one embodiment, the present invention includes a method for depositing a barrier layer on a substrate having a trench, depositing a liner layer on the barrier layer that includes a surface oxide, electrolessly depositing a copper seed layer on the liner layer, where the surface oxide is reduced in-situ in an electroless bath, depositing a bulk metal layer on the copper seed layer. Other embodiments are described and claimed.
    Type: Application
    Filed: March 1, 2007
    Publication date: September 4, 2008
    Inventors: Ramanan Chebiam, Chin-Chang Cheng, Damian Whitney, Harsono Simka
  • Publication number: 20070148952
    Abstract: Methods of fabricating interconnect structures utilizing barrier material layers formed with an electroless deposition technique utilizing a coupling agent complexed with a catalytic metal and structures formed thereby. The fabrication fundamentally comprises providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, bonding the coupling agent to the dielectric material within the opening, and electrolessly depositing the barrier material layer, wherein the electrolessly deposited barrier material layer material adheres to the catalytic metal of the coupling agent.
    Type: Application
    Filed: December 23, 2005
    Publication date: June 28, 2007
    Inventors: Kevin O'Brien, Chin-Chang Cheng, Ramanan Chebiam, Valery Dubin, Sridhar Balakrishnan
  • Publication number: 20070065585
    Abstract: A method of forming an electrolessly deposited copper interconnect while reducing its electrical resistance comprises providing a substrate having a dielectric layer, wherein a trench portion including at least two sidewall surfaces and a bottom surface is etched into the dielectric layer, depositing a copper seed layer onto the substrate and within the trench portion, attaching a layer of a metal catalyst to the substrate and within the trench portion using a coupling agent, applying ultraviolet radiation to the trench portion to detach the metal catalyst from the sidewall surfaces and the bottom surface of the trench portion, activating the metal catalyst that remains attached to the substrate, performing an electroless plating process to deposit copper into the trench portion, and planarizing the deposited copper to form an interconnect. The result is a copper interconnect that is not contaminated with a metal catalyst that may increase its electrical resistance.
    Type: Application
    Filed: September 21, 2005
    Publication date: March 22, 2007
    Inventors: Ramanan Chebiam, Arnel Fajardo
  • Publication number: 20070004587
    Abstract: A method of forming metal on a substrate includes forming a coupling agent with nitrogen on a substrate, forming a first layer containing a Ruthenium catalyst over the coupling agent, and depositing a second layer including a metal over the first layer using the Ruthenium catalyst as a nucleating agent.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventors: Ramanan Chebiam, Mike Goldstein
  • Publication number: 20060044759
    Abstract: An apparatus that includes an electroosmotic pump and an aqueous or nonaqueous electrolyte liquid and generates relatively low amount of hydrogen gas is described herein. The apparatus may further include a hydrogen absorber.
    Type: Application
    Filed: August 26, 2004
    Publication date: March 2, 2006
    Inventors: Ramanan Chebiam, Valery Dubin
  • Publication number: 20050161828
    Abstract: A method and apparatus for a semiconductor device having a semiconductor device having increased conductive material reliability is described. That method and apparatus comprises forming a conductive path on a substrate. The conductive path made of a first material. A second material is then deposited on the conductive path. Once the second material is deposited on the conductive path, the diffusion of the second material into the conductive path is facilitated. The second material has a predetermined solubility to substantially diffuse to grain boundaries within the first material.
    Type: Application
    Filed: March 9, 2005
    Publication date: July 28, 2005
    Inventors: Valery Dubin, Ramanan Chebiam
  • Publication number: 20050090098
    Abstract: A method and apparatus for a semiconductor device having a semiconductor device having increased conductive material reliability is described. That method and apparatus comprises forming a conductive path on a substrate. The conductive path made of a first material. A second material is then deposited on the conductive path. Once the second material is deposited on the conductive path, the diffusion of the second material into the conductive path is facilitated. The second material has a predetermined solubility to substantially diffuse to grain boundaries within the first material.
    Type: Application
    Filed: October 27, 2003
    Publication date: April 28, 2005
    Inventors: Valery Dubin, Ramanan Chebiam
  • Publication number: 20040262772
    Abstract: Embodiments of a method of bonding wafers together using a metal interlayer deposited on conductors of each wafer. Also disclosed is a wafer stack formed according to the method of wafer bonding using a metal interlayer.
    Type: Application
    Filed: June 30, 2003
    Publication date: December 30, 2004
    Inventors: Shriram Ramanathan, Ramanan Chebiam, Mauro J. Kobrinsky, Valery Dubin, Scott List