Patents by Inventor Ramanath Ganapathiraman

Ramanath Ganapathiraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8758717
    Abstract: A method of cutting, thinning, welding and chemically functionalizing multiwalled carbon nanotubes (CNTs) with carboxyl and allyl moieties, and altering the electrical properties of the CNT films by applying high current densities combined with air-exposure is developed and demonstrated. Such welded high-conductance CNT networks of functionalized CNTs could be useful for device and sensor applications, and may serve as high mechanical toughness mat fillers that are amenable to integration with nanocomposite matrices.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: June 24, 2014
    Assignee: Rensselaer Polytechnic Institute
    Inventors: Ramanath Ganapathiraman, Saurabh Agrawal, Raghuveer S. Makala
  • Publication number: 20100159236
    Abstract: An article includes a first surface, a second surface, and a molecular nanolayer located at an interface between the first and the second surface, where an interface toughness is a higher than 20 J m?2.
    Type: Application
    Filed: November 21, 2007
    Publication date: June 24, 2010
    Inventors: Ramanath Ganapathiraman, Darshan D. Gandhi
  • Publication number: 20090311556
    Abstract: A nanoparticle includes a metal core and an outer shell. The metal core includes a magnetic alloy of platinum and at least one additional metal. The outer shell is selected from the group consisting of silica, titania, metal nitride, and metal sulfide.
    Type: Application
    Filed: April 13, 2007
    Publication date: December 17, 2009
    Inventors: Ramanath Ganapathiraman, Qingyu Yan, Arup Purkayastha
  • Publication number: 20080292531
    Abstract: A method of cutting, thinning, welding and chemically functionalizing multiwalled carbon nanotubes (CNTs) with carboxyl and allyl moieties, and altering the electrical properties of the CNT films by applying high current densities combined with air-exposure is developed and demonstrated. Such welded high-conductance CNT networks of functionalized CNTs could be useful for device and sensor applications, and may serve as high mechanical toughness mat fillers that are amenable to integration with nanocomposite matrices.
    Type: Application
    Filed: October 18, 2007
    Publication date: November 27, 2008
    Inventors: Ramanath GANAPATHIRAMAN, Saurabh AGRAWAL, Raghuveer S. MAKALA
  • Publication number: 20080089829
    Abstract: Controllably aligned carbon nanotubes are grown, without the use of a predeposition catalyst, on electrically conducting templates that form an electrical contact with the nanotubes. The method allows fabrication of nanotube-based devices with built-in back-side electrical contacts on silicon and other substrate surfaces.
    Type: Application
    Filed: October 13, 2006
    Publication date: April 17, 2008
    Inventors: Ramanath Ganapathiraman, Saurabh Agrawal, Matthew J. Frederick, Raghuveer Makala
  • Publication number: 20070116635
    Abstract: A method of transforming a carbon single wall nanotube (SWNT) is provided. The method comprises exposing the SWNT to light having a power sufficient to ignite or reconstruct the SWNT such that the SWNT is ignited or reconstructed by the exposure to the light.
    Type: Application
    Filed: July 7, 2006
    Publication date: May 24, 2007
    Inventors: Pulickel Ajayan, Ramanath Ganapathiraman, Andres Guardia
  • Patent number: 7217404
    Abstract: A method of transforming a carbon single wall nanotube (SWNT) is provided. The method comprises exposing the SWNT to light having a power sufficient to ignite or reconstruct the SWNT such that the SWNT is ignited or reconstructed by the exposure to the light.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: May 15, 2007
    Assignee: Rensselaer Polytechnic Institute
    Inventors: Pulickel M. Ajayan, Ramanath Ganapathiraman, Andres de la Guardia
  • Patent number: 7202159
    Abstract: The present invention provides a method for forming a diffusion barrier layer, a diffusion barrier in an integrated circuit and an integrated circuit. The method for forming a diffusion barrier involves the following steps: 1) preparing a silicon substrate; 2) contacting the silicon substrate with a composition comprising self-assembled monolayer subunits and a solvent; and, 3) removing the solvent. The diffusion barrier layer includes a self-assembled monolayer. The integrated circuit includes a silicon substrate, a diffusion barrier layer and a metal deposited on the diffusion barrier layer. The diffusion barrier layer in the integrated circuit is covalently attached to the silicon substrate and includes a self-assembled monolayer.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: April 10, 2007
    Assignee: Rensselaer Polytechnic Institute
    Inventors: Ramanath Ganapathiraman, Ahila Krishnamoorthy, Kaushik Chanda, Shyam P. Murarka
  • Patent number: 7189430
    Abstract: A method of controllably aligning carbon nanotubes to a template structure to fabricate a variety of carbon nanotube containing structures and devices having desired characteristics is provided. The method allows simultaneous, selective growth of both vertically and horizontally controllably aligned nanotubes on the template structure but not on a substrate in a single process step.
    Type: Grant
    Filed: February 11, 2003
    Date of Patent: March 13, 2007
    Assignee: Rensselaer Polytechnic Institute
    Inventors: Pulickel M. Ajayan, Ramanath Ganapathiraman, Anyuan Cao
  • Publication number: 20070035226
    Abstract: Hybrid structures include aligned carbon nanotube bundles grown on curved surfaces such as micro sized or nano sized particles or bulk substrates having micro size or nano sized protrusions. The morphology of the hybrid structures can controlled by varying the size and packing of the particles or protrusions.
    Type: Application
    Filed: March 21, 2006
    Publication date: February 15, 2007
    Inventors: Ramanath Ganapathiraman, Saurabh Agrawal
  • Patent number: 7081674
    Abstract: The present invention provides a diffusion barrier useful in an integrated circuit, which serves to prevent the migration of material from a conductive layer to the underlying substrate and further provides improved adhesion of the conductive layer to the substrate. The diffusion barrier comprises a polymer which is a polyelectrolyte, having both cationic and anionic groups along its backbone chain. Preferred polyelectolyte barriers are polyethyleneimine (PEI) and polyacrylic acid (PAA). Other polyelectrolytes may be used, such as those that contain SH—OH— aromatic groups, or those that can interact with either the metal or the adjacent layers via covalent interactions and cross-linking (e.g., POMA, PSMA). The polymeric layer may be applied in two coatings, so that the amine side chains contact the dielectric (e.g. silicon) substrate and the acidic groups are adjacent to the overlying metallic interconnect (e.g. copper).
    Type: Grant
    Filed: June 11, 2004
    Date of Patent: July 25, 2006
    Assignee: Rensselaer Polytechnic Institute
    Inventors: Ramanath Ganapathiraman, Ravindra S. Kane, Gopal Ganesan Pethuraja
  • Publication number: 20050001317
    Abstract: The present invention provides a diffusion barrier useful in an integrated circuit, which serves to prevent the migration of material from a conductive layer to the underlying substrate and further provides improved adhesion of the conductive layer to the substrate. The diffusion barrier comprises a polymer which is a polyelectrolyte, having both cationic and anionic groups along its backbone chain. Preferred polyelectolyte barriers are polyethyleneimine (PEI) and polyacrylic acid (PAA). Other polyelectrolytes may be used, such as those that contain SH— OH— aromatic groups, or those that can interact with either the metal or the adjacent layers via covalent interactions and cross-linking (e.g., POMA, PSMA). The polymeric layer may be applied in two coatings, so that the amine side chains contact the dielectric (e.g. silicon) substrate and the acidic groups are adjacent to the overlying metallic interconnect (e.g. copper).
    Type: Application
    Filed: June 11, 2004
    Publication date: January 6, 2005
    Inventors: Ramanath Ganapathiraman, Ravindra Kane, Gopal Pethuraja
  • Publication number: 20030183504
    Abstract: A method of transforming a carbon single wall nanotube (SWNT) is provided. The method comprises exposing the SWNT to light having a power sufficient to ignite or reconstruct the SWNT such that the SWNT is ignited or reconstructed by the exposure to the light.
    Type: Application
    Filed: February 19, 2003
    Publication date: October 2, 2003
    Applicant: Rensselaer Polytechnic Institute
    Inventors: Pulickel M. Ajayan, Ramanath Ganapathiraman, Andres de la Guardia
  • Patent number: 5963828
    Abstract: A method in a semiconductor process for forming a layer of a selected compound on a substrate of a semiconductor device. A layer of titanium is formed on the substrate as a sacrificial layer. The layer of titanium is reduced using a gaseous form of a fluorine containing compound in which the fluorine containing compound includes the selected compound that is to be formed on the substrate of the semiconductor device.
    Type: Grant
    Filed: December 23, 1996
    Date of Patent: October 5, 1999
    Assignee: LSI Logic Corporation
    Inventors: Derryl D.J. Allman, Verne C. Hornback, Ramanath Ganapathiraman, Leslie H. Allen