Abstract: A system for reducing skew in the parallel transmission of digital data slices is provided. The system includes a transmitter unit comprising a plurality of transmitter memory devices. Control logic provides a strobe signal to each transmitter unit memory device to implement the transfer of a desired number of data characters from the transmitter unit to a receiver unit. Both its associated data slice and the strobe signal are transferred from each transmitter unit memory device to the bus via an associated transmitter unit bus driver. Each data slice and its associated strobe signal are then transferred from the bus to a corresponding receiver unit memory device via a corresponding receiver unit bus receiver device. Each receiver unit memory device includes means for generating a "receiver-full" status signal that indicates that all data slices transferred from the corresponding transmitter unit memory device have been received.

Abstract: An integrated circuit has a first resistor and a second resistor. A base-emitter voltage differential is maintained across the first resistor to develop a first resistor current and a base-emitter voltage is maintained across the second resistor to develop a second resistor current. The first resistor current is mirrored and the second resistor current is subtracted from the mirrored current to obtain a reference current. The resistors have resistance values so that the products of each resistor current multiplied by its temperature coefficient are equal. The resulting reference current is temperature independent.

Abstract: A digital bus backplane is disclosed that has interface circuitry located on the backplane. The backplane includes a backplane circuit board containing signal bus lines each operable for conducting electrical signals, several connectors each physically coupled to the backplane circuit board and each operable for electrically contacting the signal pins of a daughter board inserted into the connector, and many transceivers each physically coupled to the backplane circuit board and each electrically connected between one of the contact pins of a connector and one of the signal bus lines, where each transceiver is operable for relaying electrical signals between a daughter board and a signal bus line.

Abstract: A circuit (100) is shown which provides a large turn-on current drive to the base of a lateral PNP transistor (218) by forcing a large voltage drop across the base-emitter junction of the lateral PNP transistor in order to quickly turn on the PNP transistor. A current sensing circuit (203, 166) determines when the collector current in the PNP transistor is sufficient for proper operation of the rest of the circuitry dependent upon this PNP transistor. The current sensing circuitry then limits the base drive applied to the PNP transistor to the current level necessary to maintain the required quiescent collector current in the PNP transistor. In addition, means (190, 200) are provided to quickly clamp the base of the PNP transistor to the emitter of the PNP transistor thereby quickly turning off the PNP transistor.

Abstract: An improved driver for differentially driving a differentially conducting cable (e.g., for Ethernet) minimizes the output offset signal coupled to the cable when the driver is idle. When driven to an idle state, the driver provides a shaped output which transitions to a quiescent output level in a manner which eliminates output signal common mode step change and consequently reduces signal distortion on the cable due to reflection of the step change.

Abstract: A digital PLL technique to provide an effective sampling interval and resolution shorter than the driver clock period. A multi-phase driver clock provides a clock signals phase-offset from each other. One clock output signal is used as the driver clock to clock an input sampler. A pattern of bit samples before, nominally at, and after a predicted clock edge indicates whether a leading or lagging phase should be substituted for the present driver clock signal. The phase difference is substantially less than the period of the fastest clock presently available to generate satisfactory shaped pulses.

Abstract: In a peripheral driver circuit a switching output transistor is operated from digital logic control and is provided with a shut off circuit which turns the output transistor off when its collector supply current exceeds its saturation current. A controlled base drive current is generated in a circuit that includes a scaled reference transistor that is operated at the same current density and the same collector voltage as the output transistor at its rated current. The reference transistor base current is amplified in a circuit having a current gain equal to the scaling between the reference and output transistors. Thus the base current applied to the output transistor is related to the driver rated current which ensures that saturation will occur up to at least the rated current and above which the shut off will be effective.

Abstract: An inverter gate using advanced low power Schottky configuration is shown in which a feedback transistor is used to provide input pull up action. The transistor is a minimum area device that occupies less chip area than the elements that it replaces. It also conserves power so that the speed power product is reduced. The circuit further incorporates negative feedback associated with the input bias resistor whereby a smaller resistor can be employed without increasing supply current drain or input current.

Abstract: A bubble sense amplifier has a biasing circuit for adjusting the bias currents through magneto-resistive detectors so as to establish a preferred common mode operating voltage across the bubble detectors. The preamplifier is coupled through a junction capacitance circuit to a clamp-and-strobe circuit and to a differential comparator. The differential comparator has a selectable threshold voltage, and compares the differential bubble signal to the selected threshold voltage.

Abstract: A data bus transceiver reduces self-induced noise by using trapezoidal drive waveforms. A differential receiver stage of the transceiver has a threshold voltage matched to the midpoint voltage of the drive waveform to reduce distortion, and a low-pass filter matched to the slew rate of the drive waveform to reduce noise while causing minimum progation delay. The transceiver has been integrated using back-to-back junction capacitors in the driver and filter circuits and these capacitors have been biased to reduce their variation in capacitance as a function of the voltage applied across them.