Patents by Inventor Ramanathan Muthiah

Ramanathan Muthiah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240004573
    Abstract: A data storage device comprising a non-volatile storage medium configured to store user data, a data port configured to transmit data between a host computer system and the data storage device, a display system, and a controller. The controller is configured to receive and execute one or more commands from the host computer system to cause a data transfer between the host computer system and the storage medium of the data storage device. The controller generates performance data representing the performance of the data storage device, wherein the performance data includes an efficiency ratio value representing a relative utilization of an operational capability of the data storage device in conducting the data transfer. The controller generates one or more control signals to cause the display system to visually indicate at least the efficiency ratio value of the performance data.
    Type: Application
    Filed: June 29, 2022
    Publication date: January 4, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventor: Ramanathan MUTHIAH
  • Publication number: 20230418738
    Abstract: Latch-based methods and apparatus for performing neural network weight parity detection on the die of a non-volatile memory (NVM) array to detect bit flip errors within neural network weight data are described, particularly for use with floating point number values. Upon detection of a parity error in a neural network weight, the erroneous weight is set to zero to trim the corresponding neuron from the network, thus preventing the erroneous value from significantly affecting the network, particularly in situations where the bit flip would otherwise affect the magnitude of a floating-point weight value. The exemplary latch-based procedures described herein are linear procedures that do not require logic decisions. Procedures are also described that assess an amount of degradation in the NVM array based on parity bit data collected in the latches. Multiple plane and multiple die NVM array implementations are also described for massive parallel processing.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 28, 2023
    Inventors: Daniel Joseph Linnen, Ramanathan Muthiah, Kirubakaran Periyannan
  • Publication number: 20230418741
    Abstract: Devices and techniques are disclosed wherein an end user can remotely trigger direct data management activities of a data storage device (DSD), such as creating a data snapshot, resetting a snapshot, and setting permissions at the DSD via a remote mobile device app interface.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Balaji Thraksha Venkataramanan
  • Publication number: 20230418481
    Abstract: Noise injection procedures implemented on the die of a non-volatile memory (NVM) array are disclosed. In one example, noise is injected into data by adjusting read voltages to induce bit flips while using feedback to achieve a target amount of information degradation. In another example, random data is iteratively combined with itself to achieve a target percentage of random 1s or 0s, then the random data is combined with data read from the NVM array. In other examples, pixels are randomly zeroed out to emulate dead charge coupled device (CCD) pixels. In still other examples, the timing, voltage, and/or current values used within circuits while transferring data to/from latches or bitlines are adjusted outside their specified margins to induce bit flips to inject noise into the data. The noise-injected data may be used, for example, for dataset augmentation or for the testing of deep neural networks (DNNs).
    Type: Application
    Filed: June 22, 2022
    Publication date: December 28, 2023
    Inventors: Daniel Joseph Linnen, Kirubakaran Periyannan, Ramanathan Muthiah
  • Publication number: 20230418477
    Abstract: A data storage device comprising a non-volatile storage medium configured to store user data, a data port configured to transmit data between a host computer system and the data storage device, a data security indicator, and a controller. The controller is configured to selectively control access of the host computer system to the user data based on security configuration data of the data storage device. The controller is further configured to respond to the occurrence of one or more operations, the operations being any of: (i) a data access operation requested or performed, by the host computer system, on the data storage device to access the storage medium via the data port; and (ii) a security control operation requested or performed, by an external device, on the data storage device to store, retrieve or update the security configuration data of the data storage device.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventor: Ramanathan MUTHIAH
  • Publication number: 20230418518
    Abstract: Example storage systems, data storage devices, and methods provide redundant array of independent disk (RAID) control among peer storage devices. A master storage device among peer storage devices receives host commands and determines, based on a peer RAID configuration, data blocks for redundantly storing the host data unit among the peer storage devices. The master storage device allocates the data blocks among the peer storage devices and sends them to the peer storage devices using a peer communication channel.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Inventors: Judah Gamliel Hahn, Ramanathan Muthiah
  • Publication number: 20230418600
    Abstract: Latch-based multiply-accumulate (MAC) operations implemented on the die of a non-volatile memory (NVM) array are disclosed. The exemplary latch-based MAC procedures described herein are linear procedures that do not require logic branches. In one example, the MAC operation uses a set of linear MAC stages, wherein each linear stage processes MAC operations corresponding to one bit of a first multi-bit multiplicand being multiplied against a second multi-bit multiplicand. Examples are provided wherein the MAC procedures are performed as part of a neural network feedforward procedure where the first multiplicand is a synaptic weight and the second multiplicand is an activation value. Multiple plane and multiple die NVM array implementations are also described for massive parallel processing.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 28, 2023
    Inventors: Daniel Joseph Linnen, Ramanathan Muthiah, Kirubakaran Periyannan
  • Publication number: 20230418490
    Abstract: Example storage systems, data storage devices, and methods provide rate levelling among peer storage devices. A master storage device among peer storage devices receives host commands, determines the workload states of the peer storage devices, divides the data units in the host commands into data blocks for data striping, allocates the data blocks among the peer storage devices, and sends the data blocks to the peer storage devices using a peer communication channel.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 28, 2023
    Inventors: Ramanathan Muthiah, Judah Gamliel Hahn
  • Publication number: 20230419464
    Abstract: Bit-flip object insertion techniques are provided for use with a non-volatile memory (NVM) wherein an object is inserted into a background image by flipping or inverting one or more bits within the pixels of the background image that correspond to the shape and insertion location of an object being inserted. In an illustrative example, pixels within the background image that correspond to the shape and insertion location of the object are XORed with binary 1s. This flips the bits of those pixels to change the color (hue) and/or intensity (brightness) of the pixels so the object appears in the background image. In other examples, only the most significant bits of pixels in the background image are inverted (flipped). Exemplary latch-based procedures are described herein for high-speed processing on an NVM die. Multiple plane NVM die implementations are also described for massive processing.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 28, 2023
    Inventors: Daniel Joseph Linnen, Ramanathan Muthiah, Kirubakaran Periyannan, Nikita Thacker
  • Publication number: 20230420006
    Abstract: Noise injection procedures implemented on the die of a non-volatile memory (NVM) array are disclosed. In one example, noise is injected into data by adjusting read voltages to induce bit flips while using feedback to achieve a target amount of information degradation. In another example, random data is iteratively combined with itself to achieve a target percentage of random 1s or 0s, then the random data is combined with data read from the NVM array. In other examples, pixels are randomly zeroed out to emulate dead charge coupled device (CCD) pixels. In still other examples, the timing, voltage, and/or current values used within circuits while transferring data to/from latches or bitlines are adjusted outside their specified margins to induce bit flips to inject noise into the data. The noise-injected data may be used, for example, for dataset augmentation or for the testing of deep neural networks (DNNs).
    Type: Application
    Filed: June 22, 2022
    Publication date: December 28, 2023
    Inventors: Daniel Joseph Linnen, Kirubakaran Periyannan, Ramanathan Muthiah, Grant Chapman Mackey
  • Publication number: 20230409236
    Abstract: Disclosed are systems and methods providing active time-based prioritization in host-managed stream devices. The method includes receiving a plurality of host commands from a host system. The method also includes computing active times of open memory regions. The method also includes determining one or more regions that have remained open for more than a threshold time period, based on the active times. The method also includes prioritizing one or more host commands from amongst the plurality of host commands for completion, the one or more host commands having corresponding logical addresses belonging to the one or more regions, thereby (i) minimizing risk to data and (ii) releasing resources corresponding to the one or more regions.
    Type: Application
    Filed: June 15, 2022
    Publication date: December 21, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ramanathan MUTHIAH, Judah Gamliel HAHN, Rotem SELA
  • Publication number: 20230409470
    Abstract: Aspects of a data storage device are provided that optimize utilization of a scratchpad memory. The data storage device includes an NVM and a controller which allocates a memory location of the NVM as scratchpad memory for a host. The controller receives a command including data from a submission queue associated with the scratchpad memory, stores the data in the scratchpad memory, and disables first updates to the L2P mapping table for the data in the scratchpad memory across power cycles. The controller also receives commands from other submission queues for other memory locations than the scratchpad memory, stores data in the other memory locations, and stores second updates to a L2P mapping table. The first and second updates may include different data lengths. Thus, the device accounts for differences between scratchpad memory and NVM in at least data alignment, L2P granularity, and response, resulting in efficient scratchpad memory management.
    Type: Application
    Filed: June 15, 2022
    Publication date: December 21, 2023
    Inventor: Ramanathan MUTHIAH
  • Patent number: 11849186
    Abstract: A data storage device and method for enabling metadata-based seek points for media access are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to identify a plurality of frames in video data that differ from surrounding frames by more than a threshold amount; store identifiers of the plurality of frames in the memory; and send the identifiers to the host to enable quick playback of the video data by the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: December 19, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ramkumar Ramamurthy, Ramanathan Muthiah
  • Publication number: 20230401004
    Abstract: Disclosed are systems and methods for proactively, instead of reactively, biasing parameters of a data storage device based on a spatial position in a storage enclosure. The method includes obtaining a spatial position for the data storage device in a storage enclosure. The method also includes proactively biasing one or more parameters for controlling the device memory, based on the spatial position. The spatial position has a corresponding thermal profile that is predetermined.
    Type: Application
    Filed: June 14, 2022
    Publication date: December 14, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ramanathan MUTHIAH, Sridhar SABESAN, Dinesh BABU, Pavan GURURAJ
  • Publication number: 20230400988
    Abstract: A data storage device having improved protections for in-flight data during a safety event, such as an autonomous-driving-vehicle collision. In an example embodiment, in response to a distress-mode indication signal, the device controller operates to prioritize more-recent data with respect to older counterparts of the same data stream for flushing from the volatile-memory buffers to the non-volatile memory. In addition, the device controller may operate to positively bias the flushed data towards better survivability and/or more-reliable routing.
    Type: Application
    Filed: June 14, 2022
    Publication date: December 14, 2023
    Inventors: Ramanathan Muthiah, Julian Vlaiko, Judah Gamliel Hahn
  • Publication number: 20230403433
    Abstract: A data storage device and method for enabling metadata-based seek points for media access are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to identify a plurality , of frames in video data that differ from surrounding frames by more than a threshold amount; store identifiers of the plurality of frames in the memory; and send the identifiers to the host to enable quick playback of the video data by the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Application
    Filed: June 14, 2022
    Publication date: December 14, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ramkumar Ramamurthy, Ramanathan Muthiah
  • Publication number: 20230401005
    Abstract: Example storage systems, storage devices, and methods provide proactive management of storage operations using thermal states. Host storage requests are received and used to determine storage commands for a data storage device. For each storage command, a temperature index value corresponding to an estimated change in thermal state for executing the storage command may be determined. The storage commands are allocated to command queues based on the thermal index values and then executed from the command queues by the data storage device without triggering thermal throttling of storage commands.
    Type: Application
    Filed: June 14, 2022
    Publication date: December 14, 2023
    Inventor: Ramanathan Muthiah
  • Publication number: 20230393640
    Abstract: A data storage device and method for energy feedback and report generation are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to maintain an association between logical addresses and application identifiers of applications on a host; determine power implications associated with a command to access a logical address of the memory; generate a report on the power implications, wherein the report identifies an application identifier associated with the logical address; and provide the report to the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventor: Ramanathan Muthiah
  • Publication number: 20230385211
    Abstract: A data storage device and method for lane selection based on thermal conditions are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to determine that action is needed to control a thermal state of the data storage device; and in response to determining that action is needed to control the thermal state of the data storage device, send a request to a host to reduce a number of lanes the host uses to communicate with the data storage device, wherein reducing the number of lanes reduces an amount of heat generated by the data storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 30, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Yogesh Tayal, Anil Kumar Kolar Narayanappa
  • Publication number: 20230385148
    Abstract: Devices, systems, and methods with proactive data loss notification and handling. A data storage device includes a memory and a controller. The controller includes a processor and controller memory. The controller memory stores a set of instructions that, when executed by the processor, instruct the controller to: detect an uncorrectable error correction code (UECC) during an internal data movement process of the storage device memory, modify a metadata field associated with a logical block address corresponding to the UECC, inform a host device about the UECC, and determine whether data stored in at least one adjacent region to the logical block address is lost.
    Type: Application
    Filed: May 24, 2022
    Publication date: November 30, 2023
    Inventors: Bhavya Krishna, Ramanathan Muthiah