Patents by Inventor Ramanathan Raghavan

Ramanathan Raghavan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6285974
    Abstract: One aspect of the invention relates to a method for detecting architectural violations in a multiprocessor computer system. In one version of the invention, the method includes the steps of generating a testcase instruction stream having a plurality of instructions, executable by the processors, which access a memory which is shared by the processors; detecting dependent instructions in the testcase instruction stream; and modifying the testcase instruction stream by inserting logging instructions in the testcase in the testcase instruction stream which cause data associated with observable instructions to be written to a logging memory by writing a first sequence of unique monotonically increasing values to the memory.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: September 4, 2001
    Assignee: International Business Machines Corporation
    Inventors: Sriram Mandyam, Brian Walter O'Krafka, Ramanathan Raghavan, Robert James Ramirez, Miwako Tokugawa
  • Patent number: 5928334
    Abstract: One aspect of the invention relates to a method for detecting synchronization violations in a multiprocessor computer system having a memory location which controls access to a portion of memory shared by the processors, the memory location having at least one lock bit indicating whether the portion of memory is locked by one of the processors and a plurality of bits for storing a data value. The method comprises reading the memory location by an individual processor; testing the lock bit to determine whether the portion of memory is locked; if the portion of memory is not locked; asserting the lock bit to indicate the portion of memory is locked; incrementing the data value to represent a global access count; writing the lock bit and the data value back to the memory location; and incrementing a data value stored in a memory location associated with the individual processor to indicate an individual access count by the individual processor.
    Type: Grant
    Filed: March 28, 1997
    Date of Patent: July 27, 1999
    Assignee: International Business Machines Corporation
    Inventors: Sriram Mandyam, Brian Walter O'Krafka, Ramanathan Raghavan, Robert James Ramirez, Miwako Tokugawa
  • Patent number: 5740353
    Abstract: A method and apparatus for creating a multiprocessor verification environment. A Multiprocessor Test Generator (MPTG) generates a set of test cases in a Multiprocessor Test Language (MTL) format subject to constraints and enumeration controls in a test specification. An abstract system model of the machine under test is inputted to the Multiprocessor Test Generator. The Multiprocessor Test Generator (MPTG) receives the test specification and abstract system model, accesses a system specific database and generates test cases based on the constraints in the test specification in a Multiprocessor Test Language (MTL). The Multiprocessor Test Language (MTL) test cases are inputted to a Multiprocessor Test Executive (MPX) which controls the issuance of the test cases to a cache-coherent multiprocessor system, and monitors their completion in order to verify operation of the cache-coherent multiprocessor system.
    Type: Grant
    Filed: December 14, 1995
    Date of Patent: April 14, 1998
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey Thomas Kreulen, Sriram Srinivasan Mandyam, Brian Walter O'Krafka, Shahram Salamian, Ramanathan Raghavan
  • Patent number: 5680577
    Abstract: A method and system for processing multiple requests for data residing at the same memory address. The multiple requests are associated with an individual duplicate bit flag that indicates whether the request can be processed. Thus, manipulation of the duplicate bit flag controls the order of processing for each of the received requests, thereby maintaining data coherency and integrity.
    Type: Grant
    Filed: April 27, 1995
    Date of Patent: October 21, 1997
    Assignee: International Business Machines Corporation
    Inventors: Steven George Aden, Kai Cheng, Jin Chin Wang, Ramanathan Raghavan
  • Patent number: 5452457
    Abstract: In one aspect, a software development technique is capable of efficiently organizing for execution a conditional code segment having multiple associated conditional paths. The development technique employs in association with each path of the code segment, a probability compiler directive which dictates to the compiler a probability for satisfying a conditional test of the associated path. In another aspect, a system/process is capable of optimizing organization of assembled program code for a code's particular execution environment. This optimization approach tunes assembled code organization for each specific execution environment, employing run-time based statistical data collected during performance execution of the assembled code. The execution environment, consisting of hardware, software, and other factors such as workload, input data, etc., can also be collected and employed by an optimizer unit to best reorganize the assembled program code for a current execution environment.
    Type: Grant
    Filed: January 29, 1993
    Date of Patent: September 19, 1995
    Assignee: International Business Machines Corporation
    Inventors: Alan I. Alpert, Paul G. Greenstein, John T. Rodell, Ramanathan Raghavan