Patents by Inventor Ramanathan Ramani
Ramanathan Ramani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11476760Abstract: In some examples, a system includes a voltage source terminal, a voltage reference terminal, a field effect transistor (FET), a current source, a comparator, and adjustment circuitry. The FET has a gate terminal and a non-gate terminal, the gate terminal coupled to the voltage source terminal. The current source is coupled to the non-gate terminal. The comparator has a comparator output and first and second comparator inputs, the first comparator input coupled to the non-gate terminal, and the second comparator input coupled to the voltage reference terminal. The adjustment circuitry has a circuitry input and a circuitry output, the circuitry input coupled to the comparator output, and the adjustment circuitry configured to adjust the circuitry output responsive to the circuitry input, in which the adjustment reduces a drive strength of the circuit.Type: GrantFiled: July 13, 2020Date of Patent: October 18, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Robert Allan Neidorff, Saurav Bandyopadhyay, Ramanathan Ramani
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Patent number: 11211865Abstract: A series capacitor buck converter includes a first half-bridge circuit including a first high side power switch (HSA) and first low side power switch (LSA) connected in series having a first switching node (SWA) therebetween which drives a first output inductor, a second half-bridge circuit including a second HS power switch (HSB) and second LS power switch (LSB) connected in series having a second switching node (SWB) therebetween which drives a second output inductor. A transfer capacitor (Ct) is connected in series with HSA and LSA and between the first and second half-bridge circuits. A first current source is coupled for precharging Ct with a charging current (I_in) and a second current source is coupled to Ct for providing an output current (I_out). A feedback network providing negative feedback forces I_out to match I_in.Type: GrantFiled: February 24, 2020Date of Patent: December 28, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Joseph Maurice Khayat, Sergio Carlo-Rodriquez, Michael G. Amaro, Ramanathan Ramani, Pradeep S. Shenoy
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Publication number: 20210013805Abstract: In some examples, a system includes a voltage source terminal, a voltage reference terminal, a field effect transistor (FET), a current source, a comparator, and adjustment circuitry. The FET has a gate terminal and a non-gate terminal, the gate terminal coupled to the voltage source terminal. The current source is coupled to the non-gate terminal. The comparator has a comparator output and first and second comparator inputs, the first comparator input coupled to the non-gate terminal, and the second comparator input coupled to the voltage reference terminal. The adjustment circuitry has a circuitry input and a circuitry output, the circuitry input coupled to the comparator output, and the adjustment circuitry configured to adjust the circuitry output responsive to the circuitry input, in which the adjustment reduces a drive strength of the circuit.Type: ApplicationFiled: July 13, 2020Publication date: January 14, 2021Inventors: Robert Allan NEIDORFF, Saurav BANDYOPADHYAY, Ramanathan RAMANI
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Publication number: 20200195143Abstract: A series capacitor buck converter includes a first half-bridge circuit including a first high side power switch (HSA) and first low side power switch (LSA) connected in series having a first switching node (SWA) therebetween which drives a first output inductor, a second half-bridge circuit including a second HS power switch (HSB) and second LS power switch (LSB) connected in series having a second switching node (SWB) therebetween which drives a second output inductor. A transfer capacitor (Ct) is connected in series with HSA and LSA and between the first and second half-bridge circuits. A first current source is coupled for precharging Ct with a charging current (I_in) and a second current source is coupled to Ct for providing an output current (I_out). A feedback network providing negative feedback forces I_out to match I_in.Type: ApplicationFiled: February 24, 2020Publication date: June 18, 2020Inventors: Joseph Maurice Khayat, Sergio Carlo-Rodriquez, Michael G. Amaro, Ramanathan Ramani, Pradeep S. Shenoy
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Patent number: 10615692Abstract: A series capacitor buck converter includes a first half-bridge circuit including a first high side power switch (HSA) and first low side power switch (LSA) connected in series having a first switching node (SWA) therebetween which drives a first output inductor, a second half-bridge circuit including a second HS power switch (HSB) and second LS power switch (LSB) connected in series having a second switching node (SWB) therebetween which drives a second output inductor. A transfer capacitor (Ct) is connected in series with HSA and LSA and between the first and second half-bridge circuits. A first current source is coupled for precharging Ct with a charging current (I_in) and a second current source is coupled to Ct for providing an output current (I_out). A feedback network providing negative feedback forces I_out to match I_in.Type: GrantFiled: June 27, 2014Date of Patent: April 7, 2020Assignee: Texas Instruments IncorporatedInventors: Joseph Maurice Khayat, Sergio Carlo-Rodriquez, Michael G. Amaro, Ramanathan Ramani, Pradeep S. Shenoy
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Patent number: 9306458Abstract: A power circuit combination includes a series capacitor buck converter including a first half-bridge including a first high side power switch (HSA), first low side power switch (LSA) and a second half-bridge. A transfer capacitor (Ct) is connected in series with HSA and LSA, and between the first and second half-bridges. An adaptive HS driver circuit has an output coupled to a gate of HSA and includes a power supply circuit including a summing circuitry that dynamically outputs a variable power supply level (VGX) based on a fixed voltage and a voltage across Ct, a buffer driver, and a boost capacitor (CA) across the buffer driver. VGX is coupled to a positive terminal of CA. The power supply circuit is configured so that as a voltage across Ct varies, VGX adjusts so that a voltage across CA is changed less than a change in voltage across Ct.Type: GrantFiled: June 27, 2014Date of Patent: April 5, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Joseph Maurice Khayat, Ramanathan Ramani, Michael G. Amaro
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Publication number: 20150311794Abstract: A power circuit combination includes a series capacitor buck converter including a first half-bridge including a first high side power switch (HSA), first low side power switch (LSA) and a second half-bridge. A transfer capacitor (Ct) is connected in series with HSA and LSA, and between the first and second half-bridges. An adaptive HS driver circuit has an output coupled to a gate of HSA and includes a power supply circuit including a summing circuitry that dynamically outputs a variable power supply level (VGX) based on a fixed voltage and a voltage across Ct, a buffer driver, and a boost capacitor (CA) across the buffer driver. VGX is coupled to a positive terminal of CA. The power supply circuit is configured so that as a voltage across Ct varies, VGX adjusts so that a voltage across CA is changed less than a change in voltage across Ct.Type: ApplicationFiled: June 27, 2014Publication date: October 29, 2015Inventors: JOSEPH MAURICE KHAYAT, RAMANATHAN RAMANI, MICHAEL G. AMARO
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Publication number: 20150311793Abstract: A series capacitor buck converter includes a first half-bridge circuit including a first high side power switch (HSA) and first low side power switch (LSA) connected in series having a first switching node (SWA) therebetween which drives a first output inductor, a second half-bridge circuit including a second HS power switch (HSB) and second LS power switch (LSB) connected in series having a second switching node (SWB) therebetween which drives a second output inductor. A transfer capacitor (Ct) is connected in series with HSA and LSA and between the first and second half-bridge circuits. A first current source is coupled for precharging Ct with a charging current (I_in) and a second current source is coupled to Ct for providing an output current (I_out). A feedback network providing negative feedback forces I_out to match I_in.Type: ApplicationFiled: June 27, 2014Publication date: October 29, 2015Inventors: JOSEPH MAURICE KHAYAT, SERGIO CARLO-RODRIQUEZ, MICHAEL G. AMARO, RAMANATHAN RAMANI, PRADEEP S. SHENOY
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Patent number: 7514329Abstract: Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first portion extending partially under a gate structure between the channel and the second portion, and the second portion extending laterally between the first portion and the drain, wherein the first portion of the drift region has a concentration of first type dopants higher than the second portion.Type: GrantFiled: January 4, 2006Date of Patent: April 7, 2009Assignee: Texas Instruments IncorporatedInventors: Sameer Pendharkar, Ramanathan Ramani, Taylor R. Efland
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Patent number: 7238986Abstract: Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first portion extending partially under a gate structure between the channel and the second portion, and the second portion extending laterally between the first portion and the drain, wherein the first portion of the drift region has a concentration of first type dopants higher than the second portion.Type: GrantFiled: May 3, 2004Date of Patent: July 3, 2007Assignee: Texas Instruments IncorporatedInventors: Sameer Pendharkar, Ramanathan Ramani, Taylor R. Efland
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Publication number: 20060113592Abstract: Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first portion extending partially under a gate structure between the channel and the second portion, and the second portion extending laterally between the first portion and the drain, wherein the first portion of the drift region has a concentration of first type dopants higher than the second portion.Type: ApplicationFiled: January 4, 2006Publication date: June 1, 2006Inventors: Sameer Pendharkar, Ramanathan Ramani, Taylor Efland
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Publication number: 20050253191Abstract: Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first portion extending partially under a gate structure between the channel and the second portion, and the second portion extending laterally between the first portion and the drain, wherein the first portion of the drift region has a concentration of first type dopants higher than the second portion.Type: ApplicationFiled: May 3, 2004Publication date: November 17, 2005Inventors: Sameer Pendharkar, Ramanathan Ramani, Taylor Efland
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Patent number: 6784493Abstract: A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array.Type: GrantFiled: June 11, 2002Date of Patent: August 31, 2004Assignee: Texas Instruments IncorporatedInventors: Taylor R. Efland, David A. Grant, Ramanathan Ramani, Dale Skelton, David D. Briggs, Chin-Yu Tsai
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Patent number: 6770935Abstract: An array (90) of transistors (50) formed in a p-type layer (34), and including a second heavily doped p-type region (56) laterally extending proximate the drain of each transistor to collect minority carriers of the transistors. A deep n-type region (16) is formed in the p-type layer (34) and proximate a n-type buried layer (14) together forming a guardring about the drain regions of the plurality of transistors. The array of transistors may be interconnected in parallel to form a large power FET, whereby the heavily doped second p-type region (56) reduces the minority carrier lifetime proximate the drains of the transistors. The guardring (14, 16) collects the minority carriers (T1) and is isolated from the drains of the transistors. Preferably, the transistors are formed in a P-epi tank that is isolated by the guardring. The P-epi tank is preferably formed upon a buried NBL layer, and the deep n-type region is an N+ well extending to the buried NBL layer.Type: GrantFiled: June 11, 2002Date of Patent: August 3, 2004Assignee: Texas Instruments IncorporatedInventors: Taylor R. Efland, David A. Grant, Ramanathan Ramani, Chin-Yu Tsai, Dale Skelton
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Patent number: 6710427Abstract: A distributed power device (100) including a plurality of tank regions (90) separated from one another by a deep n-type region (16), and having formed in each tank region a plurality of transistors (50). The plurality of transistors (50) in each tank region are interconnected to transistors in other tank regions to form a large power FET, whereby the deep n-type regions isolate the tank regions from one another. A first parasitic diode (D5) is defined from each tank region to a buried layer, and a second parasitic diode (D4) is defined between the buried layer and a substrate. The deep n-type regions distribute the first and second parasitic diodes with respect to the plurality of tank regions, preferably comprised of a P-epi tank. The deep n-type regions also distribute the resistance of an NBL layer (14) formed under the tank regions.Type: GrantFiled: June 11, 2002Date of Patent: March 23, 2004Assignee: Texas Instruments IncorporatedInventors: Taylor R. Efland, David A. Grant, Ramanathan Ramani, Chin-Yu Tsai, David D. Briggs, Dale Skelton
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Patent number: 6709900Abstract: A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array.Type: GrantFiled: June 11, 2002Date of Patent: March 23, 2004Assignee: Texas Instruments IncorporatedInventors: Taylor R. Efland, David A. Grant, Ramanathan Ramani, Dale Skelton, David D. Briggs, Chin-Yu Tsai
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Publication number: 20030228721Abstract: A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array.Type: ApplicationFiled: June 11, 2002Publication date: December 11, 2003Inventors: Taylor R. Efland, David A. Grant, Ramanathan Ramani, Dale Skelton, David D. Briggs, Chin-Yu Tsai
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Publication number: 20030227070Abstract: A distributed power device (100) including a plurality of tank regions (90) separated from one another by a deep n-type region (16), and having formed in each tank region a plurality of transistors (50). The plurality of transistors (50) in each tank region are interconnected to transistors in other tank regions to form a large power FET, whereby the deep n-type regions isolate the tank regions from one another. A first parasitic diode (D5) is defined from each tank region to a buried layer, and a second parasitic diode (D4) is defined between the buried layer and a substrate. The deep n-type regions distribute the first and second parasitic diodes with respect to the plurality of tank regions, preferably comprised of a P-epi tank. The deep n-type regions also distribute the resistance of an NBL layer (14) formed under the tank regions.Type: ApplicationFiled: June 11, 2002Publication date: December 11, 2003Inventors: Taylor R. Efland, David A. Grant, Ramanathan Ramani, Chin-Yu Tsai, David D. Briggs, Dale Skelton
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Publication number: 20030228729Abstract: A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array.Type: ApplicationFiled: June 11, 2002Publication date: December 11, 2003Inventors: Taylor R. Efland, David A. Grant, Ramanathan Ramani, Dale Skelton, David D. Briggs, Chin-Yu Tsai
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Publication number: 20030228730Abstract: An array (90) of transistors (50) formed in a p-type layer (34), and including a second heavily doped p-type region (56) laterally extending proximate the drain of each transistor to collect minority carriers of the transistors. A deep n-type region (16) is formed in the p-type layer (34) and proximate a n-type buried layer (14) together forming a guardring about the drain regions of the plurality of transistors. The array of transistors may be interconnected in parallel to form a large power FET, whereby the heavily doped second p-type region (56) reduces the minority carrier lifetime proximate the drains of the transistors. The guardring (14, 16) collects the minority carriers (T1) and is isolated from the drains of the transistors. Preferably, the transistors are formed in a P-epi tank that is isolated by the guardring. The P-epi tank is preferably formed upon a buried NBL layer, and the deep n-type region is an N+ well extending to the buried NBL layer.Type: ApplicationFiled: June 11, 2002Publication date: December 11, 2003Inventors: Taylor R. Efland, David A. Grant, Ramanathan Ramani, Chin-Yu Tsai, Dale Skelton