Abstract: Various systems and methods for implementing dynamic logic are disclosed herein. For example, some embodiments of the present invention provide systems for encrypting/decrypting data. Such systems include a hardware key, a memory, a hardware decoder and a message encoder. The memory includes an encoded encoding key that represents an original encoding key. The hardware decoder receives a portion of the encoded encoding key and decodes the portion of the encoded encoding key using the hardware key to recover a portion of the original encoding key. The message encoder receives a data set and the portion of the original encoding key and encodes the data set using the portion of the original encoding key to create an encoded data set.

Abstract: Apparatus and method to scramble data prior to placing it on a bus or in memory uses embedded hardware keys for encryption/decryption. The hardware keys may be used in addition to software encryption. Different hardware keys may be used to process most significant bits and least significant bits of a data word. Different hardware keys may be used to process messages from/to different channels. The hardware key may be comprise a series of fixed logic cells.

Abstract: Various systems and methods for implementing dynamic logic are disclosed herein. For example, some embodiments of the present invention provide systems for encrypting/decrypting data. Such systems include a hardware key, a memory, a hardware decoder and a message encoder. The memory includes an encoded encoding key that represents an original encoding key. The hardware decoder receives a portion of the encoded encoding key and decodes the portion of the encoded encoding key using the hardware key to recover a portion of the original encoding key. The message encoder receives a data set and the portion of the original encoding key and encodes the data set using the portion of the original encoding key to create an encoded data set.

Abstract: Apparatus and method to scramble data prior to placing it on a bus or in memory uses embedded hardware keys for encryption/decryption. The hardware keys may be used in addition to software encryption. Different hardware keys may be used to process most significant bits and least significant bits of a data word. Different hardware keys may be used to process messages from/to different channels. The hardware key may be comprise a series of fixed logic cells.

Abstract: A digital display unit which receives horizontal lines of unequal length in a V-active region and computes an average length of the lines. The average is used to generate horizontal line demarkers in the V-blank (vertical blank) region. The demarkers specify the transition from one line to the other. Such a feature is useful in spread spectrum clocking (SSC) based display signals in which HSYNC signals may also not be available to determine the transitions from one line to another in the V-blank region.

Abstract: A digital display unit which receives horizontal lines of unequal length in a V-active region and computes an average length of the lines. The average is used to generate horizontal line demarkers in the V-blank (vertical blank) region. The demarkers specify the transition from one line to the other. Such a feature is useful in spread spectrum clocking (SSC) based display signals in which HSYNC signals may also not be available to determine the transitions from one line to another in the V-blank region.