Abstract: A method for reconstructing an aggregate stream of cells transmitted over communication links in an asynchronous transfer mode protocol includes determining a respective link delay for each of the communication links, including determining a fastest communication link. A common starting cell at which the cells from the communication links will correspond in time is determined based upon the fastest communication link. The method further includes filling a respective delay compensation buffer with corresponding cells for each of the communication links beginning with the common starting cell. The cells are read from the delay compensation buffers in a round-robin fashion to reconstruct the aggregate stream of cells.

Abstract: Problems associated with variations in pulse amplitude due to, for example, intersymbol interference, which can otherwise create problems in timing recovery circuits using the edges of the pulses are overcome by basing timing recovery on the center of the received pulses rather than the leading or trailing edges. Although jitter due to variations in pulse amplitude is not eliminated, timing recovery is improved because jitter due to variations in the center of the pulse are less than is jitter in the edges of the pulse.

Abstract: Briefly, in accordance with one embodiment of the invention, a refined timing recovery circuit for retiming a recovered data signal comprises a data pulse edge detector. The recovered data signal is derived from a received data pulse. The data pulse edge detector is adapted to be coupled to an oversampling clock. The data pulse edge detector is further adapted to sense the next clock pulse edge having the closest temporal proximity after a selected received data pulse edge. In accordance with another embodiment, an integrated circuit comprises: a timing recovery system for retiming a recovered data signal derived from a received data pulse, the timing recovery system comprising a refined timing recovery circuit. The refined timing recovery circuit includes a data pulse edge detector.

Abstract: Briefly, in accordance with the embodiment of the invention, a refined timing recovery circuit for retiming a colored data signal comprises a data pulse edge detector. The recovered data signal is derived from a received data pulse. The data pulse edge detector is adapted to be coupled to an oversampling clock. The data pulse edge detector is further adapted to sense the next clock pulse edge having the closest temporal proximity after a selected received data pulse edge. In accordance with another embodiment, an integrated circuit comprises: a timing recovery system for retiming a recovered data signal derived from a received data pulse, the timing recovery system comprising a refined timing recovery circuit. The refined timing recovery circuit includes a data pulse edge detector.

Abstract: A method of detecting whether a valid DS1 signal is being received by a receiver. If the receiver does not have a valid signal (loss of signal), then the receiver reads consecutive fixed sized N bit blocks of the received digital signal. Each of the blocks or windows is checked for minimum 1s density. Received consecutive 0s are counted and checked against a maximum. If two sequential blocks of bits satisfy the 1s and consecutive 0s tests, then the received signal is judged valid and an acquisition of signal flag is asserted.

Abstract: A method of detecting whether a valid DS1 signal is being received by a receiver. If the receiver does not have a valid signal (loss of signal), then the receiver reads consecutive fixed sized N bit blocks of the received digital signal. Each of the blocks or windows is checked for minimum 1s density. Received consecutive 0s are counted and checked against a maximum. If two sequential blocks of bits satisfy the 1s and consecutive 0s tests, then the received signal is judged valid and an acquisition of signal flag is asserted.