Patents by Inventor Ramasubramanian Rajamani
Ramasubramanian Rajamani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10859627Abstract: A processor, including: a core; system test circuitry, the system test circuitry to be locked during operational processor operation; reset circuitry including a kick-off test (KOT) input, the reset circuitry to detect a reset with the KOT input asserted, and to initiate an in-field system test (IFST) mode; a test interface controller to receive in IFST mode an encrypted test packet having a signature, verify the signature of the test packet, and decrypt the test packet; and IFST control circuitry to cause the system test circuitry to perform an IFST test according to the decrypted test packet and to log or report results.Type: GrantFiled: June 29, 2017Date of Patent: December 8, 2020Assignee: Intel CorporationInventors: Sreejit Chakravarty, Oscar Mendoza, Ramasubramanian Rajamani, Bryan J. Gran, Sorin Iacobovici, Neel Shah, Michael Neve de Mevergnies, John Cruz Mejia, Amy L. Santoni
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Patent number: 10491381Abstract: A processor, including: a core; system test circuitry, the system test circuitry configured to be locked except during an in-field system test (IFST) mode; IFST control circuitry; and a test interface controller, including: a data interface to receive a test packet; a parser to parse the test packet into a key, a signature, and a stored hash-of-hashes; a decryption circuit to decrypt the signature according to the key and to generate a computed hash-of-hashes; a hash circuit to verify the stored hash-of-hashes against the computed hash-of-hashes; and an IFST interface, wherein the test interface controller is to signal the IFST control circuitry to place the system test circuitry in IFST mode.Type: GrantFiled: June 29, 2017Date of Patent: November 26, 2019Assignee: Intel CorporationInventors: Neel Shah, Kirk S. Yap, Amy L. Santoni, Michael Neve de Mevergnies, Oscar Mendoza, Sreejit Chakravarty, Ramasubramanian Rajamani, Bryan J. Gran, Sorin Iacobovici
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Publication number: 20190004112Abstract: A processor, including: a core; system test circuitry, the system test circuitry to be locked during operational processor operation; reset circuitry including a kick-off test (KOT) input, the reset circuitry to detect a reset with the KOT input asserted, and to initiate an in-field system test (IFST) mode; a test interface controller to receive in IFST mode an encrypted test packet having a signature, verify the signature of the test packet, and decrypt the test packet; and IFST control circuitry to cause the system test circuitry to perform an IFST test according to the decrypted test packet and to log or report results.Type: ApplicationFiled: June 29, 2017Publication date: January 3, 2019Inventors: Sreejit Chakravarty, Oscar Mendoza, Ramasubramanian Rajamani, Bryan J. Gran, Sorin Iacobovici, Neel Shah, Michael Neve de Mevergnies, John Cruz Mejia, Amy L. Santoni
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Publication number: 20190007200Abstract: A processor, including: a core; system test circuitry, the system test circuitry configured to be locked except during an in-field system test (IFST) mode; IFST control circuitry; and a test interface controller, including: a data interface to receive a test packet; a parser to parse the test packet into a key, a signature, and a stored hash-of-hashes; a decryption circuit to decrypt the signature according to the key and to generate a computed hash-of-hashes; a hash circuit to verify the stored hash-of-hashes against the computed hash-of-hashes; and an IFST interface, wherein the test interface controller is to signal the IFST control circuitry to place the system test circuitry in IFST mode.Type: ApplicationFiled: June 29, 2017Publication date: January 3, 2019Inventors: Neel Shah, Kirk S. Yap, Amy L. Santoni, Michael Neve de Mevergnies, Oscar Mendoza, Sreejit Chakravarty, Ramasubramanian Rajamani, Bryan J. Gran, Sorin Iacobovici
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Patent number: 8166218Abstract: An integrated circuit to serialize local data and selectively merge it with serialized feed-through data into a serial data stream output that includes a parallel-in-serial-out (PISO) shift register, a multiplexer, and a transmitter. The PISO shift register serializes parallel data on a local data bus into serialized local data. The multiplexer selectively merges serialized local data and feed-through data into a serial data stream. The transmitter drives the serial data stream onto a serial data link. In another embodiment of the invention, a method for a memory module includes receiving an input serial data stream; merging local frames of data and feed-through frames of data together into an output serial data stream in response to a merge enable signal; and transmitting the output serial data stream on a northbound data output to a next memory module or a memory controller. Other embodiments of the invention are disclosed and claimed.Type: GrantFiled: May 23, 2008Date of Patent: April 24, 2012Assignee: Intel CorporationInventor: Ramasubramanian Rajamani
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Publication number: 20090013108Abstract: An integrated circuit to serialize local data and selectively merge it with serialized feed-through data into a serial data stream output that includes a parallel-in-serial-out (PISO) shift register, a multiplexer, and a transmitter. The PISO shift register serializes parallel data on a local data bus into serialized local data. The multiplexer selectively merges serialized local data and feed-through data into a serial data stream. The transmitter drives the serial data stream onto a serial data link. In another embodiment of the invention, a method for a memory module includes receiving an input serial data stream; merging local frames of data and feed-through frames of data together into an output serial data stream in response to a merge enable signal; and transmitting the output serial data stream on a northbound data output to a next memory module or a memory controller. Other embodiments of the invention are disclosed and claimed.Type: ApplicationFiled: May 23, 2008Publication date: January 8, 2009Inventor: Ramasubramanian Rajamani
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Patent number: 7321997Abstract: A buffer logic within a memory module having the capability to carry out a test of another memory module to which it is coupled via a point-to-point bus through autonomously storing and transmitting a test pattern across that point-to-point bus to the other memory module, while further employing another buffer logic that is interposed between the two memory modules to pass on the test pattern, but intercept a signal received from the other memory module during the test and pass on an indication of the receipt of that signal to an analysis device to monitor the test.Type: GrantFiled: March 30, 2004Date of Patent: January 22, 2008Assignee: Intel CorporationInventors: David Zimmerman, Edward Weaver, Ramasubramanian Rajamani
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Publication number: 20060195631Abstract: An integrated circuit to serialize local data and selectively merge it with serialized feed-through data into a serial data stream output that includes a parallel-in-serial-out (PISO) shift register, a multiplexer, and a transmitter. The PISO shift register serializes parallel data on a local data bus into serialized local data. The multiplexer selectively merges serialized local data and feed-through data into a serial data stream. The transmitter drives the serial data stream onto a serial data link. In another embodiment of the invention, a method for a memory module includes receiving an input serial data stream; merging local frames of data and feed-through frames of data together into an output serial data stream in response to a merge enable signal; and transmitting the output serial data stream on a northbound data output to a next memory module or a memory controller. Other embodiments of the invention are disclosed and claimed.Type: ApplicationFiled: January 31, 2005Publication date: August 31, 2006Inventor: Ramasubramanian Rajamani
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Patent number: 7047475Abstract: A sending node of a networked system includes an encoding module configured to receive a series of data groups with each data group comprising a data block comprising data bits, and control/status bits including at least one error status bit having a state indicative of a presence or absence of at least one type of data block error. The sending node is configured to generate for at least one of the data groups of the series an expected cyclic redundancy code (CRC) comprising a plurality of bits that is a function of the data block and control/status bits, not including the at least one error status bit. The sending node is further configured to encode the expected CRC with the state of the at least one error status bit to thereby generate for the at least one data group an encoded CRC comprising a plurality of bits.Type: GrantFiled: February 4, 2003Date of Patent: May 16, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Debendra Das Sharma, Ramasubramanian Rajamani
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Publication number: 20050223303Abstract: A buffer logic within a memory module having the capability to carry out a test of another memory module to which it is coupled via a point-to-point bus through autonomously storing and transmitting a test pattern across that point-to-point bus to the other memory module, while further employing another buffer logic that is interposed between the two memory modules to pass on the test pattern, but intercept a signal received from the other memory module during the test and pass on an indication of the receipt of that signal to an analysis device to monitor the test.Type: ApplicationFiled: March 30, 2004Publication date: October 6, 2005Inventors: David Zimmerman, Edward Weaver, Ramasubramanian Rajamani
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Publication number: 20040153952Abstract: A sending node of a networked system includes an encoding module configured to receive a series of data groups with each data group comprising a data block comprising data bits, and control/status bits including at least one error status bit having a state indicative of a presence or absence of at least one type of data block error. The sending node is configured to generate for at least one of the data groups of the series an expected cyclic redundancy code (CRC) comprising a plurality of bits that is a function of the data block and control/status bits, not including the at least one error status bit. The sending node is further configured to encode the expected CRC with the state of the at least one error status bit to thereby generate for the at least one data group an encoded CRC comprising a plurality of bits.Type: ApplicationFiled: February 4, 2003Publication date: August 5, 2004Inventors: Debendra Das Sharma, Ramasubramanian Rajamani