Patents by Inventor Ramaswamy Parthasarathy
Ramaswamy Parthasarathy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12137517Abstract: A wave launcher may include a printed circuit board (PCB) that includes a pin that receives a radio frequency (RF) signal. The wave launcher may include a cylinder configured to be electrically coupled to the pin and define an opening. The cylinder may receive the RF signal from the pin, form a transition from coplanar to Goubau line structure with a plate, and generate the surface wave. The wave launcher may include an insulator configured to be physically positioned within the opening and between the cylinder and a power line. The insulator may mechanically isolate the cylinder from the power line and permit the cylinder to launch the surface wave on the power line. The wave launcher may include the plate electrically coupled to a pad and may provide a reference for the pin and the cylinder. The pin and the cylinder may be physically positioned proximate the plate.Type: GrantFiled: June 22, 2021Date of Patent: November 5, 2024Assignee: Intel CorporationInventors: Vishram Shriram Pandit, Neel Harkishin Bhatia, Rajiv Panigrahi, Ramaswamy Parthasarathy, Satish Ramachandra, Ajay Sharma, Manish Sharma, Vaibhavdeep Singh, Ravichandra Tungani Chikkabasavaiah, Jayprakash Thakur
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Publication number: 20240186206Abstract: Systems, apparatuses and methods may provide for technology that includes a voltage regulator, a board assembly including a die and a circuit board electrically coupled to a first side of the die, and a thermal dissipation assembly thermally and electrically coupled to a second side of the die, wherein the thermal dissipation assembly is further electrically coupled to the voltage regulator. In one example, the thermal dissipation assembly includes a vapor chamber and the technology further includes a plurality of copper plates electrically coupled to the voltage regulator and a package substrate containing the die, wherein the plurality of copper plates are further thermally coupled to the vapor chamber.Type: ApplicationFiled: February 10, 2024Publication date: June 6, 2024Inventors: Satish PRATHABAN, Ramaswamy PARTHASARATHY, Biswajit PATRA, Tongyan ZHAI, Jeff KU, Min Suet LIM, Yi HUANG, Kai XIAO, Gene F. YOUNG, Weimin SHI
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Patent number: 11450936Abstract: A communication system communicates data elements on a conducting wire. In an embodiment, a sequence of data elements to be transmitted is electrically represented on a pair of terminals, and a transmission element located at a first portion of the conducting wire transmits the sequence in the form of a wave on a surface of the conducting wire. The transmission element includes a first conductor wrapped around the first portion of the conducting wire, a first insulator located between the first conductor and the first portion of the conducting wire, and a conductive structure disposed around the first conductor. The conductive structure has a narrow cross section at one end and extends outwardly to a broader cross section at the other end. A first terminal of the pair of terminals is electrically connected to the first conductor and the second terminal is electrically connected to the conductive structure.Type: GrantFiled: September 24, 2020Date of Patent: September 20, 2022Assignee: Intel CorporationInventors: Ramaswamy Parthasarathy, Punit Ashok Rathod, Jayprakash Thakur, Arvind Sundaram, Ajay Sharma, Nikita Bipin Ambasana, Satish Ramachandra, Vishram Shriram Pandit
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Patent number: 11340287Abstract: Embodiments include a method of stress testing an electronics package with components that include a visual indicator. In an embodiment, the method comprises populating a plurality of components on an electronics package. In an embodiment, the plurality of components each comprise a visual indicator that is responsive to heat. In an embodiment, the method further comprises stress testing the electronics package and categorizing the plurality of components based on the visual indicators. In an embodiment, the method may further comprise modifying the plurality of components.Type: GrantFiled: July 25, 2018Date of Patent: May 24, 2022Assignee: Intel CorporationInventors: Ramaswamy Parthasarathy, Vikas Rao, Praveen Pai
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Publication number: 20220132654Abstract: A wave launcher may include a printed circuit board (PCB) that includes a pin that receives a radio frequency (RF) signal. The wave launcher may include a cylinder configured to be electrically coupled to the pin and define an opening. The cylinder may receive the RF signal from the pin, form a transition from coplanar to Goubau line structure with a plate, and generate the surface wave. The wave launcher may include an insulator configured to be physically positioned within the opening and between the cylinder and a power line. The insulator may mechanically isolate the cylinder from the power line and permit the cylinder to launch the surface wave on the power line. The wave launcher may include the plate electrically coupled to a pad and may provide a reference for the pin and the cylinder. The pin and the cylinder may be physically positioned proximate the plate.Type: ApplicationFiled: June 22, 2021Publication date: April 28, 2022Inventors: Vishram Shriram PANDIT, Neel Harkishin BHATIA, Rajiv PANIGRAHI, Ramaswamy PARTHASARATHY, Satish RAMACHANDRA, Ajay SHARMA, Manish SHARMA, Vaibhavdeep SINGH, Ravichandra TUNGANI CHIKKABASAVAIAH, Jayprakash THAKUR
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Patent number: 11290059Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.Type: GrantFiled: December 13, 2019Date of Patent: March 29, 2022Assignee: Intel CorporationInventors: Khang Choong Yong, Raymond Chong, Ramaswamy Parthasarathy, Stephen Hall, Chin Lee Kuan
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Publication number: 20210203053Abstract: A communication system communicates data elements on a conducting wire. In an embodiment, a sequence of data elements to be transmitted is electrically represented on a pair of terminals, and a transmission element located at a first portion of the conducting wire transmits the sequence in the form of a wave on a surface of the conducting wire. The transmission element includes a first conductor wrapped around the first portion of the conducting wire, a first insulator located between the first conductor and the first portion of the conducting wire, and a conductive structure disposed around the first conductor. The conductive structure has a narrow cross section at one end and extends outwardly to a broader cross section at the other end. A first terminal of the pair of terminals is electrically connected to the first conductor and the second terminal is electrically connected to the conductive structure.Type: ApplicationFiled: September 24, 2020Publication date: July 1, 2021Inventors: Ramaswamy Parthasarathy, Punit Ashok Rathod, Jayprakash Thakur, Arvind Sundaram, Ajay Sharma, Nikita Bipin Ambasana, Satish Ramachandra, Vishram Shriram Pandit
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Patent number: 10973116Abstract: Embodiments are generally directed to 3D high-inductive ground plane for crosstalk reduction. An embodiment of a printed circuit board includes a first signal trace and a second signal trace on a first layer, wherein the first signal trace and second signal trace are non-intersecting; a second layer below the first layer; a third layer below the second layer; and a three-dimensional (3D) ground plane, the 3D ground plane including a first plurality of segments on the third layer, a second plurality of segments on the second layer, and a plurality of metal vias to connect the first plurality of segments and the second plurality of segments in the ground plane.Type: GrantFiled: August 29, 2017Date of Patent: April 6, 2021Assignee: Intel CorporationInventors: Jackson Chung Peng Kong, Bok Eng Cheah, Khang Choong Yong, Ramaswamy Parthasarathy
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Patent number: 10847859Abstract: Embodiments of the present disclosure provide an arrangement for single wire communications (SWC) for an electronic device. In one instance, the arrangement may comprise a cable assembly to connect with the electronic device, wherein the cable assembly may include a wire to conduct SWC and a cover portion to cover a portion of the wire. The cover portion may comprise a ferro-dielectric material. The arrangement may further include a control logic coupled with the cable assembly, to adjust characteristics associated with the ferro-dielectric material, to tune a signal termination impedance value associated with the cable assembly. Other embodiments may be described and/or claimed.Type: GrantFiled: February 23, 2017Date of Patent: November 24, 2020Assignee: Intel CorporationInventors: Arvind Sundaram, Ramaswamy Parthasarathy, Vikas Mishra
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Publication number: 20200274491Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.Type: ApplicationFiled: December 13, 2019Publication date: August 27, 2020Applicant: Intel CorporationInventors: Khang Choong YONG, Raymond CHONG, Ramaswamy PARTHASARATHY, Stephen HALL, Chin Lee KUAN
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Patent number: 10608311Abstract: Embodiments of the present disclosure provide techniques and configurations for a cable assembly for single wire communications (SWC). In one instance, the cable assembly may comprise a wire having a wire end to couple with a signal launcher of an electronic device, and a first cover portion to house a first portion of the wire that extends from the wire end. The first cover portion may comprise a shape to conform to a shape of the signal launcher, and may be fabricated of a material with a dielectric constant above a threshold. The assembly may further comprise a second cover portion coupled with the first cover portion to house a second portion of the wire that extends from the first wire portion and protrudes from the first cover portion. The second cover portion may be fabricated of a ferrite material. Other embodiments may be described and/or claimed.Type: GrantFiled: February 23, 2017Date of Patent: March 31, 2020Assignee: Intel CorporationInventors: Arvind Sundaram, Ramaswamy Parthasarathy, Ranjul Balakrishnan, Vikas Mishra
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Publication number: 20200033401Abstract: Embodiments include a method of stress testing an electronics package with components that include a visual indicator. In an embodiment, the method comprises populating a plurality of components on an electronics package. In an embodiment, the plurality of components each comprise a visual indicator that is responsive to heat. In an embodiment, the method further comprises stress testing the electronics package and categorizing the plurality of components based on the visual indicators. In an embodiment, the method may further comprise modifying the plurality of components.Type: ApplicationFiled: July 25, 2018Publication date: January 30, 2020Inventors: Ramaswamy PARTHASARATHY, Vikas RAO, Praveen PAI
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Patent number: 10516366Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.Type: GrantFiled: December 31, 2018Date of Patent: December 24, 2019Assignee: Intel CorporationInventors: Khang Choong Yong, Raymond Chong, Ramaswamy Parthasarathy, Stephen Hall, Chin Lee Kuan
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Patent number: 10366035Abstract: A solution to the technical problem of improving device-to-device connection speeds includes the use of single-wire communication (SWC). Unlike the two differential wires required in transmission lines, SWC includes a transmission method using a single wire for data without requiring a return wire. The use of SWC has the potential to enable low loss channels of increasingly high bandwidth. The SWC improvements in bandwidth and frequency enable a significant reduction of power required for communication. SWC provides significant improvement in speed for each channel, so fewer wires may be used for each device-to-device connection. SWC also provides the ability to convey increased bandwidth and increased power over each wire, which further reduces the number of wires needed to provide power and communication.Type: GrantFiled: March 29, 2017Date of Patent: July 30, 2019Assignee: Intel CorporationInventors: Arvind Sundaram, Ramaswamy Parthasarathy, Vikas Mishra
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Publication number: 20190208620Abstract: Embodiments are generally directed to 3D high-inductive ground plane for crosstalk reduction. An embodiment of a printed circuit board includes a first signal trace and a second signal trace on a first layer, wherein the first signal trace and second signal trace are non-intersecting; a second layer below the first layer; a third layer below the second layer; and a three-dimensional (3D) ground plane, the 3D ground plane including a first plurality of segments on the third layer, a second plurality of segments on the second layer, and a plurality of metal vias to connect the first plurality of segments and the second plurality of segments in the ground plane.Type: ApplicationFiled: August 29, 2017Publication date: July 4, 2019Inventors: Jackson Chung Peng KONG, Bok Eng CHEAH, Khang Choong YONG, Ramaswamy PARTHASARATHY
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Publication number: 20190158024Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.Type: ApplicationFiled: December 31, 2018Publication date: May 23, 2019Applicant: Intel CorporationInventors: Khang Choong YONG, Raymond CHONG, Ramaswamy PARTHASARATHY, Stephen HALL, Chin Lee KUAN
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Patent number: 10171033Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.Type: GrantFiled: March 25, 2017Date of Patent: January 1, 2019Assignee: Intel CorporationInventors: Khang Choong Yong, Raymond Chong, Ramaswamy Parthasarathy, Stephen Hall, Chin Lee Kuan
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Publication number: 20180287239Abstract: A solution to the technical problem of improving device-to-device connection speeds includes the use of single-wire communication (SWC). Unlike the two differential wires required in transmission lines, SWC includes a transmission method using a single wire for data without requiring a return wire. The use of SWC has the potential to enable low loss channels of increasingly high bandwidth. The SWC improvements in bandwidth and frequency enable a significant reduction of power required for communication. SWC provides significant improvement in speed for each channel, so fewer wires may be used for each device-to-device connection. SWC also provides the ability to convey increased bandwidth and increased power over each wire, which further reduces the number of wires needed to provide power and communication.Type: ApplicationFiled: March 29, 2017Publication date: October 4, 2018Inventors: Arvind Sundaram, Ramaswamy Parthasarathy, Vikas Mishra
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Publication number: 20180241110Abstract: Embodiments of the present disclosure provide an arrangement for single wire communications (SWC) for an electronic device. In one instance, the arrangement may comprise a cable assembly to connect with the electronic device, wherein the cable assembly may include a wire to conduct SWC and a cover portion to cover a portion of the wire. The cover portion may comprise a ferro-dielectric material. The arrangement may further include a control logic coupled with the cable assembly, to adjust characteristics associated with the ferro-dielectric material, to tune a signal termination impedance value associated with the cable assembly. Other embodiments may be described and/or claimed.Type: ApplicationFiled: February 23, 2017Publication date: August 23, 2018Inventors: Arvind Sundaram, Ramaswamy Parthasarathy, Vikas Mishra
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Publication number: 20180241113Abstract: Embodiments of the present disclosure provide techniques and configurations for a cable assembly for single wire communications (SWC). In one instance, the cable assembly may comprise a wire having a wire end to couple with a signal launcher of an electronic device, and a first cover portion to house a first portion of the wire that extends from the wire end. The first cover portion may comprise a shape to conform to a shape of the signal launcher, and may be fabricated of a material with a dielectric constant above a threshold. The assembly may further comprise a second cover portion coupled with the first cover portion to house a second portion of the wire that extends from the first wire portion and protrudes from the first cover portion. The second cover portion may be fabricated of a ferrite material. Other embodiments may be described and/or claimed.Type: ApplicationFiled: February 23, 2017Publication date: August 23, 2018Inventors: Arvind Sundaram, Ramaswamy Parthasarathy, Ranjul Balakrishnan, Vikas Mishra