Patents by Inventor Rambabu Nerukonda

Rambabu Nerukonda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11755804
    Abstract: An integrated circuit includes an intellectual property core, scan data pipeline circuitry configured to convey scan data to the intellectual property core, and scan control pipeline circuitry configured to convey one or more scan control signals to the intellectual property core. The integrated circuit also includes a wave shaping circuit configured to detect a trigger event on the one or more scan control signals and, in response to detecting the trigger event, suppress a scan clock to the intellectual property core for a selected number of clock cycles.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: September 12, 2023
    Assignee: Xilinx, Inc.
    Inventors: Albert Shih-Huai Lin, Rambabu Nerukonda, Niravkumar Patel, Amitava Majumdar
  • Publication number: 20230205959
    Abstract: An integrated circuit includes an intellectual property core, scan data pipeline circuitry configured to convey scan data to the intellectual property core, and scan control pipeline circuitry configured to convey one or more scan control signals to the intellectual property core. The integrated circuit also includes a wave shaping circuit configured to detect a trigger event on the one or more scan control signals and, in response to detecting the trigger event, suppress a scan clock to the intellectual property core for a selected number of clock cycles.
    Type: Application
    Filed: December 28, 2021
    Publication date: June 29, 2023
    Applicant: Xilinx, Inc.
    Inventors: Albert Shih-Huai Lin, Rambabu Nerukonda, Niravkumar Patel, Amitava Majumdar
  • Patent number: 10969433
    Abstract: Apparatus and associated methods relate to compacting scan chain output responses of vectors into an on-chip multiple-input shift register (MISR) in the presence of unknown/indeterministic values X in design. In an illustrative example, a system may include a processing engine configured to generate a control signal for a MISR, and the control signal may hold information of what cycle has deterministic output response. The MISR may be configured to compact deterministic output responses of actual scan chain output responses in response to the decoded control signal and compare on-chip MISR signatures with expected MISR signatures to generate pass/fail status of the test. By using the system, unknown/indeterministic values X on the output responses may be blocked from being compacted into the MISR. Accordingly, the on-chip MISR signatures may not be corrupted by the unknown/indeterministic values X, and accuracy of the scan test may be advantageously improved.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: April 6, 2021
    Assignee: XILINX, INC.
    Inventors: Rambabu Nerukonda, Ismed D. Hartanto, Aaron K. Mathew