Abstract: Integrated circuit structures having varied percentage-Ge silicon germanium nanowires, and methods of fabricating integrated circuit structures having varied percentage-Ge silicon germanium nanowires, are described. For example, an integrated circuit structure includes a stack of horizontal nanowires. A lower one of the horizontal nanowires has a relatively higher percentage-Ge silicon and germanium composition. An upper one of the horizontal nanowires has a relatively lower percentage-Ge silicon and germanium composition. An intermediate horizontal nanowire is vertically between the lower one of the horizontal nanowires and the upper one of the horizontal nanowires and has an intermediate percentage-Ge silicon and germanium composition between the relatively higher percentage-Ge silicon and germanium composition and the relatively lower percentage-Ge silicon and germanium composition. A gate structure is vertically around the stack of horizontal nanowires.

Abstract: Gate-all-around integrated circuit structures having a heterogeneous or mixed cFET architecture are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires over a second vertical stack of horizontal nanowires, the first vertical stack of horizontal nanowires including (110) silicon nanowires, and the second vertical stack of horizontal nanowires including (100) silicon nanowires, or the first vertical stack of horizontal nanowires including (100) silicon nanowires, and the second vertical stack of horizontal nanowires including (110) silicon nanowires. First epitaxial source or drain structures are at ends of the first vertical stack of horizontal nanowires. Second epitaxial source or drain structures are at ends of the second vertical stack of horizontal nanowires, the second epitaxial source or drain structures vertically beneath and having a different composition than the first epitaxial source or drain structures.

Abstract: Techniques are provided herein to form gate-all-around (GAA) semiconductor devices, such as those having a stacked transistor configuration. In one example case, two different semiconductor devices may both be GAA transistors each having any number of nanoribbons extending in the same (e.g., horizontal) direction where one device is located vertically above the other device. An internal spacer structure extends between the nanoribbons of both devices along the vertical direction, where the spacer structure includes one or more rib features between the two devices. A gate structure that includes one or more gate dielectric layers and one or more gate electrode layers may be formed around the nanoribbons of both devices, in some cases. In other cases, a split-gate configuration is used where upper and lower gate structures are separated by an isolation structure. Forksheet transistors and other GAA configurations may be formed using the techniques as well.

Abstract: A dopant may included in one or more sacrificial layers, e.g., silicon layers or silicon germanium layers, used for forming nanoribbon transistors. Adding a dopant to a silicon germanium layer may cause the silicon germanium to be more stress neutral, to prevent relaxation after etching stacks of individuated nanoribbons. Alternatively, when added to one or more sacrificial layers of silicon, the doped silicon layers may counteract elastic stress from the silicon germanium layers. The dopant layers may be included at various positions in a stack of materials. The dopant layer may include one or more dopants selected from carbon, arsenic, boron, and phosphorus.

Abstract: An apparatus comprising an integrated circuit die comprising a first interconnect layer; a second interconnect layer; and a plurality of vias coupling the first interconnect layer to the second interconnect layer; wherein the first interconnect layer comprises a conductive material having a grain size of at least 100 nanometers.

Abstract: An integrated circuit includes an upper semiconductor body extending in a first direction from an upper source region to an upper drain region, and a lower semiconductor body extending in the first direction from a lower source region to a lower drain region. The upper body is spaced vertically from the lower body in a second direction orthogonal to the first direction. A gate spacer structure is adjacent to the upper and lower source regions. In an example, the gate spacer structure includes (i) a first section having a first dimension in the first direction, and (ii) a second section having a second dimension in the first direction. In an example, the first dimension is different from the second dimension by at least 1 nm. In some cases, an intermediate portion of the gate spacer structure extends laterally within a given gate structure, or between upper and lower gate structures.

Abstract: Techniques are provided herein to form semiconductor devices on a substrate with an alternative crystallographic surface orientation. The techniques are particularly useful with respect to gate-all-around and forksheet transistor configurations. A substrate having a (110) crystallographic surface orientation forms the basis for the growth of alternating types of semiconductor layers. Both n-channel and p-channel transistors may be fabricated using silicon nanoribbons formed from some of the alternating semiconductor layers. The crystallographic surface orientation of the Si nanoribbons will reflect the same crystallographic surface orientation of the substrate, which leads to a higher hole mobility across the Si nanoribbons of the p-channel devices and an overall improved CMOS device performance.

Abstract: Techniques are provided herein to form gate-all-around (GAA) semiconductor devices, such as those having a stacked transistor configuration. In one example case, two different semiconductor devices may both be GAA transistors each having any number of nanoribbons extending in the same (e.g., horizontal) direction where one device is located vertically above the other device. An internal spacer structure extends between the nanoribbons of both devices along the vertical direction, where the spacer structure includes one or more rib features between the two devices. A gate structure that includes one or more gate dielectric layers and one or more gate electrode layers may be formed around the nanoribbons of both devices, in some cases. In other cases, a split-gate configuration is used where upper and lower gate structures are separated by an isolation structure. Forksheet transistors and other GAA configurations may be formed using the techniques as well.

Abstract: Integrated circuit structures having GeSnB source or drain structures, and methods of fabricating integrated circuit structures having GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include germanium, tin and boron.