Patents by Inventor Rameen Hadizadeh

Rameen Hadizadeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200303312
    Abstract: Methods and devices for solderless integration of multiple semiconductor dies on flexible substrates. In some embodiments, a method for solderless integration of multiple semiconductor dies on flexible substrates includes arranging one or a plurality of semiconductor dies on a first carrier, active side down, and then depositing a sacrificial material over them. In some embodiments, the method further includes removing the first carrier and then building a wafer-level redistribution layer (RDL) over the active side of the one or plurality of semiconductor dies and the sacrificial material. In some embodiments, the method includes patterning the wafer-level RDL to form an outline of a final module footprint and then applying a second carrier to the wafer-level RDL. In some embodiments, the method can also include removing the sacrificial material from the one or plurality of semiconductor dies and the wafer-level RDL to achieve an integration of the one or plurality of semiconductor dies.
    Type: Application
    Filed: March 31, 2020
    Publication date: September 24, 2020
    Inventor: Rameen Hadizadeh
  • Patent number: 10679946
    Abstract: Methods and devices for solderless integration of multiple semiconductor dies on flexible substrates. In some embodiments, a method for solderless integration of multiple semiconductor dies on flexible substrates includes arranging one or a plurality of semiconductor dies on a first carrier, active side down, and then depositing a sacrificial material over them. In some embodiments, the method further includes removing the first carrier and then building a wafer-level redistribution layer (RDL) over the active side of the one or plurality of semiconductor dies and the sacrificial material. In some embodiments, the method includes patterning the wafer-level RDL to form an outline of a final module footprint and then applying a second carrier to the wafer-level RDL. In some embodiments, the method can also include removing the sacrificial material from the one or plurality of semiconductor dies and the wafer-level RDL to achieve an integration of the one or plurality of semiconductor dies.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: June 9, 2020
    Assignee: WISPRY, INC.
    Inventor: Rameen Hadizadeh
  • Publication number: 20190311989
    Abstract: Methods and devices for solderless integration of multiple semiconductor dies on flexible substrates. In some embodiments, a method for solderless integration of multiple semiconductor dies on flexible substrates includes arranging one or a plurality of semiconductor dies on a first carrier, active side down, and then depositing a sacrificial material over them. In some embodiments, the method further includes removing the first carrier and then building a wafer-level redistribution layer (RDL) over the active side of the one or plurality of semiconductor dies and the sacrificial material. In some embodiments, the method includes patterning the wafer-level RDL to form an outline of a final module footprint and then applying a second carrier to the wafer-level RDL. In some embodiments, the method can also include removing the sacrificial material from the one or plurality of semiconductor dies and the wafer-level RDL to achieve an integration of the one or plurality of semiconductor dies.
    Type: Application
    Filed: April 10, 2019
    Publication date: October 10, 2019
    Inventor: Rameen Hadizadeh
  • Publication number: 20190304938
    Abstract: The present subject matter relates to systems and methods for wafer-level manufacturing of devices having land grid array interfaces. Such devices can include a semiconductor die comprises an active surface including one or more electrical contacts, conductive studs in a directly metallized connection with the electrical contacts, an over-mold structure substantially surrounding the active surface of the semiconductor die and the conductive studs, and conductive contacts formed in an outer surface of the over-mold structure. In this configuration, each of the conductive contacts is connected to one of the conductive studs, and the conductive contacts define a land grid array interface on the outer surface of the over-mold structure.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 3, 2019
    Inventor: Rameen Hadizadeh