Patents by Inventor Rameet Pal

Rameet Pal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method, system, and computer program product for performing channel analyses for an electronic circuit design including a parallel interface
    Patent number: 10726188
    Abstract: Disclosed are methods and systems for characterizing and analyzing an electronic system design including a parallel interface. Some methods and systems identify an electronic design including a parallel interface, determine a single circuit representation including the parallel interface from the electronic design, and analyze the parallel interface to determine waveform responses of the parallel interface by using channel analysis techniques without performing circuit simulations.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 28, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Kumar Chidhambara Keshavan, Ambrish Kant Varma, Taranjit Singh Kukal, Rameet Pal, Bradford Griffin, Kenneth Robert Willis, Hui Qi, Xuegang Zeng
  • System and method for schematic-driven generation of input/output models
    Patent number: 10528688
    Abstract: Embodiments include herein are directed towards a method for generating an input/output model from a SPICE (Simulation Program with Integrated Circuit Emphasis) netlist. Embodiments may include receiving, using a processor, a SPICE netlist associated with an electronic design and selecting at least a portion of the SPICE netlist for analysis. Embodiments may further include reading the selected portion of the SPICE netlist and rendering a schematic symbol corresponding to the selected portion of the netlist. Embodiments may also include performing one or more operations associated with the schematic symbol and translating the one or more operations into simulation commands.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: January 7, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Rameet Pal, Taranjit Singh Kukal, Rajesh Prasad Singh
  • Method, system, and computer program product for performing channel analyses for an electronic circuit design including a parallel interface
    Patent number: 9798848
    Abstract: Disclosed are methods and systems for characterizing and analyzing an electronic system design including a parallel interface. Some methods and systems identify an electronic design including a parallel interface, determine a single circuit representation including the parallel interface from the electronic design, and analyze the parallel interface to determine waveform responses of the parallel interface by using channel analysis techniques without performing circuit simulations.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: October 24, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Kumar Chidhambara Keshavan, Ambrish Kant Varma, Taranjit Singh Kukal, Rameet Pal, Bradford Griffin, Kenneth Robert Willis, Hui Qi, Xuegang Zeng