Abstract: Coding circuitry for difference-based data transformation in an illustrative embodiment comprises a difference-based encoder having a plurality of processing stages, with the difference-based encoder being configured to generate respective orders of difference from a sequence of data samples and to output encoded data determined based on at least a selected one of the orders of difference. The coding circuitry may be configured to implement lossless, linear compression of the sequence of data samples. The coding circuitry may additionally or alternatively comprise a difference-based decoder having a plurality of processing stages, with the difference-based encoder being configured to process encoded data comprising selected ones of a plurality of orders of difference and to reconstruct a sequence of data samples based on the selected orders of difference.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, wherein the scan chain is separated into a plurality of scan segments with each such segment comprising a distinct subset of two or more of the plurality of scan cells. The scan test circuitry further comprises scan segment bypass circuitry configured to selectively bypass one or more of the scan segments in a scan shift mode of operation. The scan segment bypass circuitry may comprise a plurality of multiplexers and a scan segment bypass controller. The multiplexers are arranged within the scan chain and configured to allow respective ones of the scan segments to be bypassed responsive to respective bypass control signals generated by the scan segment bypass controller.

Abstract: A scan chain lockup latch comprises at least one latching element and data input control circuitry configured to control application of data to a data input of the latching element responsive to a scan enable signal. The lockup latch is configured for coupling between first and second scan cells of a scan chain. The scan chain may be controllable between a scan shift mode of operation and a functional mode of operation responsive to the scan enable signal. The data input control circuitry may be configured to maintain the data input of the latching element at a constant logic value when the scan chain is in its functional mode of operation such that switching activity in the latching element is suppressed. The scan chain lockup latch and the associated scan chain may be implemented in scan test circuitry of an integrated circuit, for testing additional circuitry of that integrated circuit.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells. The scan test circuitry further comprises scan delay defect bypass circuitry comprising a plurality of multiplexers arranged within said at least one scan chain. At least a given one of the multiplexers is configured to allow a corresponding one of the scan cells to be selectively bypassed in a scan shift configuration of the scan cells responsive to a delay defect associated with that scan cell. A delay defect bypass controller may be used to generate a bypass control signal for controlling the multiplexer between at least a first state in which the corresponding scan cell is not bypassed and a second state in which the corresponding scan cell is bypassed.

Abstract: An integrated circuit comprises divider circuitry configured to perform a division operation. The divider circuitry may be part of an arithmetic logic unit or other computational unit of a microprocessor, digital signal processor, or other type of processor. The divider circuitry iteratively determines bits of a quotient over multiple stages of computation. In determining the quotient in one embodiment, the divider circuitry is configured to estimate a partial remainder for a given one of the stages and to predict one or more of the quotient bits for one or more subsequent stages based on the estimated partial remainder so as to allow one or more computations to be skipped for said one or more subsequent stages, thereby reducing power consumption. The integrated circuit may be incorporated in a computer, a mobile telephone, a storage device or other type of processing device.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells. The scan test circuitry further comprises scan enable timing control circuitry coupled between a scan enable input of the scan test circuitry and scan enable inputs of respective ones of the scan cells. The scan enable timing control circuitry is operative to control timing of a transition between a scan shift configuration of the scan cells and a functional data capture configuration of the scan cells so as to permit testing of the scan cells in the scan shift configuration.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of sub-chains associated with respective distinct clock domains, and clock domain bypass circuitry configured to selectively bypass one or more of the sub-chains. The scan chain is configurable in a scan shift mode of operation to form a serial shift register that includes fewer than all of the sub-chains with at least a remaining one of the sub-chains being bypassed by the clock domain bypass circuitry so as to not be part of the serial shift register in the scan shift mode. By selectively bypassing portions of the scan chain associated with particular clock domains, the clock domain bypass circuitry serves to reduce test time and power consumption during scan testing.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises transition control circuitry configured to detect transitions between binary logic levels in a scan test signal, and responsive to a number of detected transitions reaching a threshold, to limit further transitions associated with a remaining portion of the scan test signal. In an illustrative embodiment, the transition control circuitry limits further transitions associated with the remaining portion of the scan test signal by replacing at least part of the remaining portion of the scan test signal with a limited transition signal. The limited transition signal may be maintained at a constant binary logic level such that it has no transitions. By limiting the number of transitions associated with the scan test signal, the transition control circuitry serves to reduce integrated circuit power consumption during scan testing.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises scan cells configured to form scan chains. At least a given one of the scan cells is a multiple scan input scan cell having at least first and second scan inputs. In a first scan shift mode of operation, the given scan cell is configured with a first plurality of other scan cells into a scan chain of a first type using the first scan input. In a second scan shift mode of operation, the given scan cell is configured with a second plurality of other scan cells different than the first plurality of other scan cells into a scan chain of a second type using the second scan input.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains, including at least one wrapper cell scan chain arranged between first and second circuitry cores of the additional circuitry, with the wrapper cell scan chain comprising a plurality of wrapper cells and being configurable to operate as a serial shift register in a scan shift mode of operation. At least one of the wrapper cells of the wrapper cell scan chain comprises a flip-flop having a throughput data path that is part of a scan shift path of the wrapper cell scan chain and not part of a functional path between the first and second circuitry cores. In an HDD controller embodiment, the first and second circuitry cores may comprise respective read channel and additional cores of a system-on-chip.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains coupled to the additional circuitry, a scan capture clock generator configured to generate a scan capture clock signal having a controllable number of capture pulses, and a clock selection circuit configured to select between at least the scan capture clock signal and a scan shift clock signal for application to clock signal inputs of the scan chains. In one embodiment, the scan capture clock generator comprises a finite state machine, a plurality of capture clock pulse circuits each generating a capture clock pulse signal comprising a different number of capture clock pulses, and logic circuitry coupled to the finite state machine and having inputs adapted to receive the outputs of the capture clock pulse circuits.

Abstract: An integrated circuit comprises scan test circuitry and additional internal circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains, with each such scan chain comprising a plurality of flip-flops configurable to operate as a serial shift register. The plurality of scan chains are arranged in sets of two or more parallel scan chains. The scan test circuitry further comprises multiplexing circuitry, including a plurality of multiplexers each associated with a corresponding one of the sets of parallel scan chains and configured to multiplex scan test outputs from the parallel scan chains within the corresponding one of the sets of parallel scan chains. In one embodiment, one or more of the sets of parallel scan chains comprise respective pairs of parallel scan chains with each such pair corresponding to a single original scan chain.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, with the scan chain being configured to operate as a serial shift register in a scan shift mode of operation and to capture functional data from at least a portion of the additional circuitry in a functional mode of operation. At least a given one of the scan cells of the scan chain comprises output control circuitry which is configured to disable a functional data output of the scan cell in the scan shift mode of operation and to disable a scan output of the scan cell in the functional mode of operation.

Abstract: A testbench for an integrated circuit (IC) design including a chain of scan circuits having a memory characteristic is verified by: (a) dividing the chain of scan circuits and creating a plurality of partitions, each partition including at least one logic cone output, each scan circuit belonging to one of the partition as a logic cone output; (b) generating a partitioned netlist for each partition from a full netlist for the IC design, the partitioned netlist including at least one logic cone, the logic cone extending from the logic cone output to at least one logic cone input; (c) generating a partitioned testbench for each partition from the full testbench based on the partitioned netlists; and (d) performing verification for the testbench by simulating the partitioned testbenches on the corresponding partitioned netlists.

Abstract: An apparatus and method are provided for identifying functionally sensitized data paths in a logic circuit and storing the identified data paths in a representation of the logic circuit. The representation of the logic circuit includes a single occurrence of each identified data path along with a variable for each single name or path segment identified. The variable represents a number of times that path segment or signal name was functionally sensitized.

Abstract: A testbench for an integrated circuit (IC) design including a chain of scan circuits having a memory characteristic is verified by: (a) dividing the chain of scan circuits and creating a plurality of partitions, each partition including at least one logic cone output, each scan circuit belonging to one of the partition as a logic cone output; (b) generating a partitioned netlist for each partition from a full netlist for the IC design, the partitioned netlist including at least one logic cone, the logic cone extending from the logic cone output to at least one logic cone input; (c) generating a partitioned testbench for each partition from the full testbench based on the partitioned netlists; and (d) performing verification for the testbench by simulating the partitioned testbenches on the corresponding partitioned netlists.

Abstract: An apparatus and method are provided for identifying functionally sensitized data paths in a logic circuit and storing the identified data paths in a representation of the logic circuit. The representation of the logic circuit includes a single occurrence of each identified data path along with a variable for each single name or path segment identified. The variable represents a number of times that path segment or signal name was functionally sensitized.