Patents by Inventor Ramesh Chidambaram

Ramesh Chidambaram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220359409
    Abstract: The present disclosure relates to methods and apparatus for forming thin-form-factor reconstituted substrates and semiconductor device packages for radio frequency applications. The substrate and package structures described herein may be utilized in high-density 2D and 3D integrated devices for 4G, 5G, 6G, and other wireless network systems. In one embodiment, a silicon substrate is structured by laser ablation to include cavities for placement of semiconductor dies and vias for deposition of conductive interconnections. Additionally, one or more cavities are structured to be filled or occupied with a flowable dielectric material. Integration of one or more radio frequency components adjacent the dielectric-filled cavities enables improved performance of the radio frequency elements with reduced signal loss caused by the silicon substrate.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Guan Huei SEE, Ramesh CHIDAMBARAM
  • Patent number: 11417605
    Abstract: The present disclosure relates to methods and apparatus for forming thin-form-factor reconstituted substrates and semiconductor device packages for radio frequency applications. The substrate and package structures described herein may be utilized in high-density 2D and 3D integrated devices for 4G, 5G, 6G, and other wireless network systems. In one embodiment, a silicon substrate is structured by laser ablation to include cavities for placement of semiconductor dies and vias for deposition of conductive interconnections. Additionally, one or more cavities are structured to be filled or occupied with a flowable dielectric material. Integration of one or more radio frequency components adjacent the dielectric-filled cavities enables improved performance of the radio frequency elements with reduced signal loss caused by the silicon substrate.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: August 16, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Guan Huei See, Ramesh Chidambaram
  • Patent number: 11289387
    Abstract: Methods and apparatus perform backside via reveal processes using a centralized control framework for multiple process tools. In some embodiments, a method for performing a backside via reveal process may include receiving process tool operational parameters from process tools involved in the backside via reveal process by a central controller, receiving sensor metrology data from at least one or more of the process tools involved in the backside via reveal process, and altering the backside reveal process based, at least in part, on the process tool operational parameters and the sensor metrology data by adjusting two or more of the process tools involved in the backside via reveal process. The profile parameters are configured to prevent backside via breakage during a chemical mechanical polishing (CMP) process.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: March 29, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Prayudi Lianto, Sik Hin Chi, Shih-Chao Hung, Pin Gian Gan, Ricardo Fujii Vinluan, Gaurav Mehta, Ramesh Chidambaram, Guan Huei See, Arvind Sundarrajan, Upendra V. Ummethala, Wei Hao Kew, Muhammad Adli Danish Bin Abdullah, Michael Charles Kutney, Mark McTaggart Wylie, Amulya Ligorio Athayde, Glen T. Mori
  • Publication number: 20220037216
    Abstract: Methods and apparatus perform backside via reveal processes using a centralized control framework for multiple process tools. In some embodiments, a method for performing a backside via reveal process may include receiving process tool operational parameters from process tools involved in the backside via reveal process by a central controller, receiving sensor metrology data from at least one or more of the process tools involved in the backside via reveal process, and altering the backside reveal process based, at least in part, on the process tool operational parameters and the sensor metrology data by adjusting two or more of the process tools involved in the backside via reveal process. The profile parameters are configured to prevent backside via breakage during a chemical mechanical polishing (CMP) process.
    Type: Application
    Filed: July 31, 2020
    Publication date: February 3, 2022
    Inventors: Prayudi LIANTO, Sik Hin CHI, Shih-Chao HUNG, Pin Gian GAN, Ricardo Fujii VINLUAN, Gaurav MEHTA, Ramesh CHIDAMBARAM, Guan Huei SEE, Arvind SUNDARRAJAN, Upendra V. UMMETHALA, Wei Hao KEW, Muhammad Adli Danish Bin ABDULLAH, Michael Charles KUTNEY, Mark McTaggart WYLIE, Amulya Ligorio ATHAYDE, Glen T. MORI
  • Publication number: 20200358163
    Abstract: The present disclosure relates to methods and apparatus for forming thin-form-factor reconstituted substrates and semiconductor device packages for radio frequency applications. The substrate and package structures described herein may be utilized in high-density 2D and 3D integrated devices for 4G, 5G, 6G, and other wireless network systems. In one embodiment, a silicon substrate is structured by laser ablation to include cavities for placement of semiconductor dies and vias for deposition of conductive interconnections. Additionally, one or more cavities are structured to be filled or occupied with a flowable dielectric material. Integration of one or more radio frequency components adjacent the dielectric-filled cavities enables improved performance of the radio frequency elements with reduced signal loss caused by the silicon substrate.
    Type: Application
    Filed: April 7, 2020
    Publication date: November 12, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Guan Huei SEE, Ramesh CHIDAMBARAM
  • Publication number: 20050215823
    Abstract: This invention relates to a process for the production of 3,3?,4,4?-tetraminobiphenyl (TAB) of formula (1) from non-carcinogenic raw materials, employing Suzuki type biaryl coupling as the key step. sMore particularly, it relates to a three steps process for the production of TAB comprising biaryl aryl coupling of 2-nitro-4-bromoacetanilide (NBA) of formula (2) catalyzed by sulfilimine based palladacycles as catalysts followed by the basic hydrolysis of acetyl group and the reduction of nitro groups with conventional reducing agents.
    Type: Application
    Filed: March 29, 2004
    Publication date: September 29, 2005
    Applicant: Council of Scientific and Industrial Research
    Inventors: Sudhir Bavikar, Asif Maner, Ramesh Chidambaram, Sudalai Arumugam, Sivaram Swaminathan