Abstract: Systems, methods, devices, and processors are described for a wireless receiver. The receiver may be configured to receive signals transmitted according to various mobile digital television standards. The receiver may include a number of hardware engines. The hardware engines may be individually controlled in a number of aspects. Power to particular hardware engines may be controlled, and the speed of the different hardware engines may vary. The receiver may include a novel multi-function decoder engine. The receiver may be configured to dynamically avoid problems related to harmonics, and may include a novel tap configuration with taps at different locations in the data flow.

Abstract: Systems, methods, devices, and processors are described for a wireless receiver. The receiver may be configured to receive signals transmitted according to various mobile digital television standards. The receiver may include a number of hardware engines. The hardware engines may be individually controlled in a number of aspects. Power to particular hardware engines may be controlled, and the speed of the different hardware engines may vary. The receiver may include a novel multi-function decoder engine. The receiver may be configured to dynamically avoid problems related to harmonics, and may include a novel tap configuration with taps at different locations in the data flow.

Abstract: Systems, methods, devices, and processors are described for a wireless receiver. The receiver may be configured to receive signals transmitted according to various mobile digital television standards. The receiver may include a number of hardware engines. The hardware engines may be individually controlled in a number of aspects. Power to particular hardware engines may be controlled, and the speed of the different hardware engines may vary. The receiver may include a novel multi-function decoder engine. The receiver may be configured to dynamically avoid problems related to harmonics, and may include a novel tap configuration with taps at different locations in the data flow.

Abstract: Systems, methods, devices, and processors are described for a wireless receiver. The receiver may be configured to receive signals transmitted according to various mobile digital television standards. The receiver may include a number of hardware engines. The hardware engines may be individually controlled in a number of aspects. Power to particular hardware engines may be controlled, and the speed of the different hardware engines may vary. The receiver may include a novel multi-function decoder engine. The receiver may be configured to dynamically avoid problems related to harmonics, and may include a novel tap configuration with taps at different locations in the data flow.

Abstract: Systems, methods, devices, and processors are described for a wireless receiver. The receiver may be configured to receive signals transmitted according to various mobile digital television standards. The receiver may include a number of hardware engines. The hardware engines may be individually controlled in a number of aspects. Power to particular hardware engines may be controlled, and the speed of the different hardware engines may vary. The receiver may include a novel multi-function decoder engine. The receiver may be configured to dynamically avoid problems related to harmonics, and may include a novel tap configuration with taps at different locations in the data flow.

Abstract: Systems, methods, devices, and processors are described for a wireless receiver. The receiver may be configured to receive signals transmitted according to various mobile digital television standards. The receiver may include a number of hardware engines. The hardware engines may be individually controlled in a number of aspects. Power to particular hardware engines may be controlled, and the speed of the different hardware engines may vary. The receiver may include a novel multi-function decoder engine. The receiver may be configured to dynamically avoid problems related to harmonics, and may include a novel tap configuration with taps at different locations in the data flow.

Abstract: Systems, devices, processors, and methods are described for tagging the reliability of received data. A frame of data is received in a digitized version of a wireless signal may be received and stored in a frame memory table. Errors within the stored portion of the frame may be searched for by accessing and processing the data from the frame memory table. In a second memory table, a memory location corresponding to a region of the first memory table may be tagged based on the search. Rows to be corrected may be identified based on the tag state for their corresponding region.

Abstract: A method and apparatus for processing channelized and unchannelized data within a signal are described. In one embodiment, a method comprises receiving in a network element, data packets within a number of channels, wherein each of the number of channels are channelized or unchannelized, processing, in a protocol engine within the network element, the data packets within the number of channels that are channelized, and processing, in the protocol engine within the network element, the data packets within the number of channels that are unchannelized.

Abstract: A method and apparatus for multiplexing and demultiplexing communication signals are described herein. In one embodiment, an apparatus includes first sample logic to sample a plurality of communication signals each including a clock component and a non-clock component. The first sample logic includes a first multiplexer to receive the clock components and a second multiplexer to receive the non-clock components. In addition, a first counter is coupled to a control input of the first multiplexer and the second multiplexer. A capture unit including a non-clock component storage element coupled to an output of the second multiplexer and edge detection logic is coupled to an output of the first multiplexer to detect a transition of a clock component and coupled to a control input of the non-clock component storage element.

Abstract: A method and apparatus for processing bytes received from a data stream includes multiple parallel byte processing engines that simultaneously process a first set of bytes received from a data channel during a first cycle and simultaneously process a second set of bytes received from the data channel during a second cycle. The method and apparatus further includes a state memory for storing byte information pertaining to the first set of bytes. When processing HDLC protocol bytes, the multiple parallel byte processing engines process the first and second set of bytes to identify at least one delineating byte contained within the data channel in accordance with a HDLC protocol.

Abstract: A method and apparatus for processing data packets of differing protocols across different channels within signals are described. In an embodiment, a method includes receiving at least one signal, wherein the at least one signal includes a number of channels such that each of the number of channels can include different protocols and different configurations for the different protocols. The method also includes processing data packets in each of the number of channels in a predefined order.

Abstract: A method and apparatus for processing bytes received from a data stream includes multiple parallel byte processing engines that simultaneously process a first set of bytes received from a data channel during a first cycle and simultaneously process a second set of bytes received from the data channel during a second cycle. The method and apparatus further includes a state memory for storing byte information pertaining to the first set of bytes. When processing HDLC protocol bytes, the multiple parallel byte processing engines process the first and second set of bytes to identify at least one delineating byte contained within the data channel in accordance with a HDLC protocol.