Patents by Inventor Ramesh Gangappa

Ramesh Gangappa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090132879
    Abstract: Techniques for efficiently performing scan tests are described. In an aspect, a single test pin may be used for both a scan input and a scan output for a scan chain. This multiplexing may reduce test costs and provide other benefits. In one design, an integrated circuit (IC) die includes a scan chain and an input/output (I/O) circuit. The I/O circuit is coupled between the scan chain and a single pad for a single test pin. The I/O circuit multiplexes a scan input and a scan output for the scan chain, provides the scan input from the pad to the scan chain during an input phase of a clock cycle, and provides the scan output from the scan chain to the pad during an output phase of the clock cycle. A bi-directional control signal controls the multiplexing of the scan input and the scan output by the I/O circuit.
    Type: Application
    Filed: August 13, 2008
    Publication date: May 21, 2009
    Applicant: QUALCOMM, INCORPORATED
    Inventor: Ramesh Gangappa