Abstract: Automating optimal placement of macro-blocks in the design of an integrated circuit. A first set of placements is generated and corresponding measures of optimalness for each placement is computed. A new set of placements is generated, with each placement being generated from multiple (“chosen placements”) of the first set of placements. The position of each macro in the new placement is made to be at least substantially identical to the position of the corresponding macro in one of the chosen placements. The placements having high values of optimalness are selected to be the chosen placements, thereby causing the properties of desirable placements to be propagated to new set of placements, as is common in genetic evolution. Another aspect of the present invention enables automatic removal of overlaps in a placement.