Abstract: A low-dropout (LDO) regulator. The LDO regulator includes a pass transistor, a charge pump connected to the pass transistor, and an error amplifier connected through the charge pump to the pass transistor, wherein the error amplifier receives a voltage VO from the pass transistor and generates a voltage VE based on the voltage VO, wherein the charge pump receives the voltage VE from the error amplifier, generates a voltage VE* that is lower than VE by an offset and supplies the voltage VE* as a gate voltage to the pass transistor.

Abstract: Devices and techniques are described in which stochastic computation is performed on analog periodic pulse signals instead of random, stochastic digital bit streams. Exploiting pulse width modulation (PWM), time-encoded signals corresponding to specific values are generated by adjusting the frequency (period) and duty cycles of PWM signals. With this approach, the latency, area, and energy consumption are all greatly reduced, as compared to prior stochastic approaches. Circuits synthesized with the proposed approach can work as fast and energy efficiently as a conventional binary design while retaining the fault-tolerance and low-cost advantages of conventional stochastic designs.

Abstract: A low-dropout (LDO) regulator. The LDO regulator includes a pass transistor, a charge pump connected to the pass transistor, and an error amplifier connected through the charge pump to the pass transistor, wherein the error amplifier receives a voltage VO from the pass transistor and generates a voltage VE based on the voltage VO, wherein the charge pump receives the voltage VE from the error amplifier, generates a voltage VE* that is lower than VE by an offset and supplies the voltage VE* as a gate voltage to the pass transistor.

Abstract: Devices and techniques are described in which stochastic computation is performed on analog periodic pulse signals instead of random, stochastic digital bit streams. Exploiting pulse width modulation (PWM), time-encoded signals corresponding to specific values are generated by adjusting the frequency (period) and duty cycles of PWM signals. With this approach, the latency, area, and energy consumption are all greatly reduced, as compared to prior stochastic approaches. Circuits synthesized with the proposed approach can work as fast and energy efficiently as a conventional binary design while retaining the fault-tolerance and low-cost advantages of conventional stochastic designs.

Abstract: Capacitors that can be formed fully on an integrated circuit (IC) chip are described in this disclosure. An IC chip includes a metal-oxide-silicone (MOS) capacitor formed from a MOS transistor having a drain terminal, a source terminal, a gate terminal, and a body terminal. The drain terminal and the source terminal are not electrically connected to any other node, and the gate terminal and the body terminal form respective first and second terminals of the MOS capacitor. The IC chip also includes an electrical conductor coupled to one of the gate terminal or the body terminal of the MOS transistor and configured to deliver a voltage to operate the MOS capacitor in an accumulation mode.

Abstract: Capacitors that can be formed fully on an integrated circuit (IC) chip are described in this disclosure. An IC chip includes a metal-oxide-silicone (MOS) capacitor formed from a MOS transistor having a drain terminal, a source terminal, a gate terminal, and a body terminal. The drain terminal and the source terminal are not electrically connected to any other node, and the gate terminal and the body terminal form respective first and second terminals of the MOS capacitor. The IC chip also includes an electrical conductor coupled to one of the gate terminal or the body terminal of the MOS transistor and configured to deliver a voltage to operate the MOS capacitor in an accumulation mode.

Abstract: A linear transform can be performed using a passive analog multi-stage charge re-use linear transform circuit. The passive analog multi-stage charge re-use linear transform circuit transforms an input analog circuit to generate a transformed analog output signal. The passive analog multi-stage charge re-use linear transform circuit may be included in a software defined radio (SDR), where the transformed analog output signal may be output to an analog-to-digital converter (ADC) of the SDR device so as to enable the ADC to perform wideband spectrum sensing. The passive analog multi-stage charge re-use linear transform circuit may also be included in a beamforming device so as to enable the device to perform spectral shifting and spatial shifting of signals. This passive analog multi-stage charge re-use linear transform circuit may promote reduced power consumption in comparison to other circuits while also supporting wideband applications at high sampling rates.

Abstract: A linear transform can be performed using a passive analog multi-stage charge re-use linear transform circuit. The passive analog multi-stage charge re-use linear transform circuit transforms an input analog circuit to generate a transformed analog output signal. The passive analog multi-stage charge re-use linear transform circuit may be included in a software defined radio (SDR), where the transformed analog output signal may be output to an analog-to-digital converter (ADC) of the SDR device so as to enable the ADC to perform wideband spectrum sensing. The passive analog multi-stage charge re-use linear transform circuit may also be included in a beamforming device so as to enable the device to perform spectral shifting and spatial shifting of signals. This passive analog multi-stage charge re-use linear transform circuit may promote reduced power consumption in comparison to other circuits while also supporting wideband applications at high sampling rates.

Abstract: A linear transform can be performed using a passive analog multi-stage charge re-use linear transform circuit. The passive analog multi-stage charge re-use linear transform circuit transforms an input analog circuit to generate a transformed analog output signal. The passive analog multi-stage charge re-use linear transform circuit may be included in a software defined radio (SDR), where the transformed analog output signal may be output to an analog-to-digital converter (ADC) of the SDR device so as to enable the ADC to perform wideband spectrum sensing. The passive analog multi-stage charge re-use linear transform circuit may also be included in a beamforming device so as to enable the device to perform spectral shifting and spatial shifting of signals. This passive analog multi-stage charge re-use linear transform circuit may promote reduced power consumption in comparison to other circuits while also supporting wideband applications at high sampling rates.

Abstract: An ultra-wideband (UWB) receiver utilizing an Xn(n>1) device as a signal detector for short pulse(s), impulse(s) or ultra-wideband signal(s). The transmitted signal comes to antenna and passes through a band pass filter (BPF). The signal is fed into an Xn device. The output signal from the Xn device is fed into integration/dump block. The output from the integration/dump block is fed into decision block.

Abstract: A VCO is based on a capacitively emitter degenerated topology which uses a cross-coupled MOS pair as the degeneration cell. The cross-coupled MOS pair contributes additional conductance and results in a higher maximum attainable oscillation frequency and better negative resistance characteristics as compared to the other topologies at high frequencies. These properties of the disclosed VCO combined with small effective capacitance enable low-power low-noise high-frequency VCO implementations.

Abstract: An ultra-wideband (UWB) receiver utilizing an Xn(n>1) device as a signal detector for short pulse(s), impulse(s) or ultra-wideband signal(s). The transmitted signal comes to antenna and passes through a band pass filter (BPF). The signal is fed into an Xn device. The output signal from the Xn device is fed into integration/dump block. The output from the integration/dump block is fed into decision block.

Abstract: In general, the disclosure is directed to techniques for enhancing power efficiency and linearity in an RF power amplifier. In accordance with the invention, a combination of different class power amplifiers is implemented in a parallel configuration to overcome the trade-off that exists between power efficiency and linearity. In particular, a class A amplifier and a class B amplifier are arranged in parallel to produce a combined amplifier output for an input signal. With bias voltages set to achieve a desired operating ratio between the class A and class B amplifier, the combined amplifier can provide a high power gain over a larger input range. In addition, the class B amplifier can provide increased power efficiency for larger inputs.

Abstract: In general, the invention is directed to integration of passive radio frequency (RF) structures with at least one integrated circuit in a single integrated circuit (IC) package. An IC package in accordance with the invention may include, for example, a radio IC, a digital IC, a passive radio frequency balun as well as additional passive RF structures or ICs. Additionally, passive electronic components may further be incorporated in the IC package. For example, the IC package may include a resistor, capacitor, inductor or the like. The components of the IC package may be distributed throughout layers of a multi-layer IC package, such as a multi-layer ceramic package. The different ICs and the passive RF structures may be electrically coupled via conductive traces, which may be varied in thickness and length in order to match input and output impedances of the different ICs and passive RF structures.

Abstract: A VCO is based on a capacitively emitter degenerated topology which uses a cross-coupled MOS pair as the degeneration cell. The cross-coupled MOS pair contributes additional conductance and results in a higher maximum attainable oscillation frequency and better negative resistance characteristics as compared to the other topologies at high frequencies. These properties of the disclosed VCO combined with small effective capacitance enable low-power low-noise high-frequency VCO implementations.

Abstract: Circuits and methods that improve linearity with use of cancellation of at least a portion, and preferably, substantially all of, at least one significant harmonic from the output of a primary circuit, e.g., the 3rd harmonic, using the output of a substantially functionally identical auxiliary circuit.

Abstract: An analog to digital method and apparatus corrects non-linearity error and gain error in a multiple stage pipeline analog to digital converter over a plurality of clock cycles. Preferably, continuous correction, during each of the plurality of clock cycles, of at least portion of non-linearity error introduced by a digital to analog conversion is performed in a first stage of the multiple stage pipeline analog to digital converter with use of an averaging over time of a first stage digital residue signal provided by the remainder stages of the multiple stage pipeline analog to digital converter. Such correction is used to provide a non-linearity corrected digital signal. Correction, during each of the plurality of clock cycles, of at least a portion of a gain error introduced by one or more amplifiers in the multiple stage pipeline analog to digital converter is provided by averaging the non-linearity corrected digital signal over time.

Abstract: The invention provides a balun for coupling an unbalanced device with a balanced device. The balun may, for example, comprise an unbalanced balun structure having a first unbalanced component and a second unbalanced component electrically coupled to one another and a balanced balun structure having a first balanced component and a second balanced component. The first balanced component electromagnetically couples more than one side of the first unbalanced component and the second balanced component electromagnetically couples more than one side of the second unbalanced component. The unbalanced and balanced components may comprise conducting strips, such as strip lines, disposed on a dielectric layer. The balun may be formed on multiple layers or only a single layer. The balun receives unbalanced signals and outputs balanced signals, i.e., signals with a 180-degree phase shift and vice versa.

Abstract: The invention provides a balun for coupling an unbalanced device with a balanced device. The balun may, for example, comprise an unbalanced balun structure having a first unbalanced component and a second unbalanced component electrically coupled to one another and a balanced balun structure having a first balanced component and a second balanced component. The first balanced component electromagnetically couples more than one side of the first unbalanced component and the second balanced component electromagnetically couples more than one side of the second unbalanced component. The unbalanced and balanced components may comprise conducting strips, such as strip lines, disposed on a dielectric layer. The balun may be formed on multiple layers or only a single layer. The balun receives unbalanced signals and outputs balanced signals, i.e., signals with a 180-degree phase shift and vice versa.

Abstract: In general, the invention is directed to integration of passive radio frequency (RF) structures with at least one integrated circuit in a single integrated circuit (IC) package. An IC package in accordance with the invention may include, for example, a radio IC, a digital IC, a passive radio frequency balun as well as additional passive RF structures or ICs. Additionally, passive electronic components may further be incorporated in the IC package. For example, the IC package may include a resistor, capacitor, inductor or the like. The components of the IC package may be distributed throughout layers of a multi-layer IC package, such as a multi-layer ceramic package. The different ICs and the passive RF structures may be electrically coupled via conductive traces, which may be varied in thickness and length in order to match input and output impedances of the different ICs and passive RF structures.