Abstract: Malformed VLAN packets can be detected by programming suitable rules in a TCAM in the packet processing pipeline. In some deployments, for example, the TCAM rule(s) can match on the parsed EtherType metadata. More specifically, the match can be based on the EtherType metadata being set to a value equal to known VLAN TPIDs, such as 0x8100, 0x88a8, rather than being set to a standard EtherType.

Abstract: A patient monitoring system includes an electroencephalography (EEG) monitor and an EEG sensor array. The EEG sensor array includes a plurality of electrodes configured to acquire EEG signals from a patient. The EEG monitor may be configured to calculate one or more depth of anesthesia indices for the patient based on received EEG signals from the EEG sensor array. Additionally, the EEG monitor may be configured to generate and display a topographic color map of the calculated depth of anesthesia indices.

Abstract: A patient monitoring system includes an electroencephalography (EEG) monitor and an EEG sensor array. The EEG sensor array includes a plurality of electrodes configured to acquire EEG signals from a patient. The EEG monitor may be configured to calculate one or more depth of anesthesia indices for the patient based on received EEG signals from the EEG sensor array. Additionally, the EEG monitor may be configured to generate and display a topographic color map of the calculated depth of anesthesia indices.

Abstract: A patient monitoring system includes an electroencephalography (EEG) monitor and an EEG sensor array. The EEG sensor array includes a plurality of electrodes configured to acquire EEG signals from a patient. The EEG monitor may be configured to calculate one or more depth of anesthesia indices for the patient based on received EEG signals from the EEG sensor array. Additionally, the EEG monitor may be configured to generate and display a topographic color map of the calculated depth of anesthesia indices.

Abstract: Systems and methods for adaptive and automated traffic engineering of data transport services may include learning the demand between devices and data paths based on application workloads, prediction of traffic demand and paths based on the workload history, provisioning and management of data paths (i.e. network links) based on the predicted demand, and real-time monitoring and data flow adaptation. Systems and methods for adaptive and automated traffic engineering of data transport services may also include learning the variation of traffic (data flow in the network) on various links (data paths) of the network topology using historical data (e.g. a minute, an hour, a day, or a week of data), predicting the data flow pattern for a time interval, and provisioning the services to steer data to meet the application requirements and other network wide goals (e.g., load balancing).

Abstract: Systems and methods for adaptive and automated traffic engineering of data transport services may include learning the demand between devices and data paths based on application workloads, prediction of traffic demand and paths based on the workload history, provisioning and management of data paths (i.e. network links) based on the predicted demand, and real-time monitoring and data flow adaptation. Systems and methods for adaptive and automated traffic engineering of data transport services may also include learning the variation of traffic (data flow in the network) on various links (data paths) of the network topology using historical data (e.g. a minute, an hour, a day, or a week of data), predicting the data flow pattern for a time interval, and provisioning the services to steer data to meet the application requirements and other network wide goals (e.g., load balancing).

Abstract: Systems and methods for automatically managing the bandwidth requirements of application workloads may include learning the bandwidth requirements using historical data, predicting the required bandwidth for a time interval and provisions the services to deliver the appropriate bandwidth to the applications. Systems and methods for automatically managing the bandwidth requirements of application workloads may also include monitoring for the actual bandwidth requirements of the applications and adapt dynamically to changing requirements.

Abstract: A patient monitoring system includes an electroencephalography (EEG) monitor and an EEG sensor array. The EEG sensor array includes a plurality of electrodes configured to acquire EEG signals from a patient. The EEG monitor may be configured to calculate one or more depth of anesthesia indices for the patient based on received EEG signals from the EEG sensor array. Additionally, the EEG monitor may be configured to generate and display a topographic color map of the calculated depth of anesthesia indices.

Abstract: The invention provides compounds containing the ring-opening products of ethylenically unsaturated cyclic carbonates for use in preparing hydrogel polymers, as well as methods for their preparation. A preferred method of the invention includes the reaction of nucleophilic compounds containing Si, F, N or O atoms, or combinations thereof, or latent moieties in the form of unsaturated or hydroxylated functional groups, with ethylenically unsaturated glycerol carbonate derivatives. The compounds and hydrogel polymers are useful for the preparation of contact lenses.

Abstract: Disclosed are new compounds having utility in applications, including as reactants and intermediates in for the formation of polymers and polymeric materials especially useful as hydrogels for ophthalmic lenses.

Abstract: In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. Using a first interrupt signal after each transfer of signal groups from the peripheral direct memory access unit, the data can be efficiently transferred from a channel memory of the peripheral direct memory access unit to the high level data link controller. A second interrupt from the high level data link controller when a last word of a packet is transferred thereto causes a new channel memory to be accessed. An abort signal is generated when a signal group for a packet being processed by the high level data link controller is not available in a timely manner.

Abstract: In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. When a packet is received by a shared high level data link controller, the data signal groups are processed and placed in a temporary storage unit. The address signal group of the received packet is applied to channel block unit where the digital signal processor subsystem, to which the packet is directed, is identified and an INTERRUPT signal corresponding to the identified digital signal processor subsystem is generated. The INTERRUPT signal is applied to a switch. The switch, which receives the signal groups from the temporary storage unit, directs the signal groups to a buffer memory in the channel associated with the identified signal processing subsystem.

Abstract: In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. Using a first interrupt signal after each transfer of signal groups from the peripheral direct memory access unit, the data can be efficiently transferred from a channel memory of the peripheral direct memory access unit to the high level data link controller. A second interrupt from the high level data link controller when a last word of a packet is transferred thereto causes a new channel memory to be accessed. An abort signal is generated when a signal group for a packet being processed by the high level data link controller is not available in a timely manner.

Abstract: In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. When a packet is received by a shared high level data link controller, the data signal groups are processed and placed in a temporary storage unit. The address signal group of the received packet is applied to channel block unit where the digital signal processor subsystem, to which the packet is directed, is identified and an INTERRUPT signal corresponding to the identified digital signal processor subsystem is generated. The INTERRUPT signal is applied to a switch. The switch, which receives the signal groups from the temporary storage unit, directs the signal groups to a buffer memory in the channel associated with the identified signal processing subsystem.

Abstract: In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. Using a first interrupt signal after each transfer of signal groups from the peripheral direct memory access unit, the data can be efficiently transferred from a channel memory of the peripheral direct memory access unit to the high level data link controller. A second interrupt from the high level data link controller when a last word of a packet is transferred thereto causes a new channel memory to be accessed.