Abstract: A contact structure in a semiconductor device includes a layer of dielectric material and a via formed through the dielectric material. The contact structure further includes a spacer formed on sidewalls of the via using atomic layer deposition (ALD) and a metal deposited in the via.

Abstract: Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided overlying the charge trapping layer and about sidewalls of the insulating members. Sidewall spacers are formed overlying the polycrystalline silicon layer and about the sidewalls of the insulating members. A portion of the first polycrystalline silicon layer and a first portion of the charge trapping layer are removed. A first insulating layer is conformally deposited overlying the insulating members and the substrate. A gate spacer is formed between the two insulating members and overlying the first insulating layer. The two insulating members are removed and the charge trapping layer is etched to form charge storage nodes. Impurity dopants are implanted into the substrate to form impurity-doped bitline regions within the substrate.

Abstract: An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.

Abstract: Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided overlying the charge trapping layer and about sidewalls of the insulating members. Sidewall spacers are formed overlying the polycrystalline silicon layer and about the sidewalls of the insulating members. A portion of the first polycrystalline silicon layer and a first portion of the charge trapping layer are removed. A first insulating layer is conformally deposited overlying the insulating members and the substrate. A gate spacer is formed between the two insulating members and overlying the first insulating layer. The two insulating members are removed and the charge trapping layer is etched to form charge storage nodes. Impurity dopants are implanted into the substrate to form impurity-doped bitline regions within the substrate.

Abstract: A method for forming an integrated circuit system is provided including forming a substrate having a core region and a periphery region, forming a charge storage stack over the substrate in the core region, forming a gate stack with a stack header having a metal portion over the substrate in the periphery region, and forming a memory system with the stack header over the charge storage stack.

Abstract: A memory system includes a substrate, forming a first insulator over the substrate, forming a charge trap layer, having a composition for setting a predetermined electrical charge level, over the first insulator, and forming a second insulator over the charge trap layer.

Abstract: A method for forming an integrated circuit system is provided including forming a substrate; forming a stack over the substrate, the stack having a sidewall and formed from a charge trap layer and a semi-conducting layer; and slot plane antenna oxidizing the stack for forming a protection enclosure having a protection layer along the sidewall.

Abstract: Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided overlying the charge trapping layer and about sidewalls of the insulating members. Sidewall spacers are formed overlying the polycrystalline silicon layer and about the sidewalls of the insulating members. A portion of the first polycrystalline silicon layer and a first portion of the charge trapping layer are removed. A first insulating layer is conformally deposited overlying the insulating members and the substrate. A gate spacer is formed between the two insulating members and overlying the first insulating layer. The two insulating members are removed and the charge trapping layer is etched to form charge storage nodes. Impurity dopants are implanted into the substrate to form impurity-doped bitline regions within the substrate.

Abstract: A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from the contacts.

Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, and slot plane antenna plasma oxidizing the charge trap layer for forming a second insulator layer.

Abstract: Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided overlying the charge trapping layer and about sidewalls of the insulating members. Sidewall spacers are formed overlying the polycrystalline silicon layer and about the sidewalls of the insulating members. A portion of the first polycrystalline silicon layer and a first portion of the charge trapping layer are removed. A first insulating layer is conformally deposited overlying the insulating members and the substrate. A gate spacer is formed between the two insulating members and overlying the first insulating layer. The two insulating members are removed and the charge trapping layer is etched to form charge storage nodes. Impurity dopants are implanted into the substrate to form impurity-doped bitline regions within the substrate.

Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer having a gradient of a silicon above and below the charge trap layer over the first insulator layer, and forming a second insulator layer over the charge trap layer.

Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a first intermediate layer over the first insulator layer, forming a charge trap layer over the first intermediate layer, forming a second intermediate layer over the charge trap layer, and forming a second insulator layer with the second intermediate layer.

Abstract: An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.

Abstract: A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.

Abstract: The present invention relates to a process for the preparation of [S(?) amlodipine-L(+)-hemi taratarte] from RS amlodipine base using L(+) tartaric acid in the presence of dimethyl sulfoxide.

Abstract: The present invention relates to of salts of 5-methoxy-2-(4-methoxy-3,5-dimethylpyridin-2-ylmethylsulfinyl) imidazo[4,5-b]pyridine (Tenatoprazole) of formula (1) wherein X is Li, Na, Ca, K or Mg and to a process for the preparation thereof which comprises oxidizing a compound of formula (2) and isolating the salt (Li, Na) by treatment with the alkali hydroxide or exchanging the sodium salt of tenatoprazole with Mg++ or Ca++ cation.

Abstract: The present invention relates to RS 1-{4-[2-(allyloxy)-ethyl]phenoxy}-3-isopropylamino propan-2-ol of the formula (1), process for preparation thereof by selective allylation of p-hydroxy phenyl ethanol and use thereof in a preparation of RS betaxolol of formula (2)

Abstract: The present invention relates to of salts of 5-methoxy-2-(4-methoxy-3,5-dimethylpyridin-2-ylmethylsulfinyl) imidazo[4,5-b]pyridine (Tenatoprazole) of formula (1) wherein X is Li, Na, Ca, K or Mg and to a process for the preparation thereof which comprises oxidizing a compound of formula (2) and isolating the salt (Li, Na) by treatment with the alkali hydroxide or exchanging the sodium salt of tenatoprazole with Mg++ or Ca++ cation.

Abstract: The present invention relates to of salts of 5-methoxy-2-(4-methoxy-3,5-dimethylpyridin-2-ylmethylsulfinyl) imidazo[4,5-b]pyridine (Tenatoprazole) of formula (1) wherein X is Li, Na, Ca, K or Mg and to a process for the preparation thereof which comprises oxidizing a compound of formula (2) and isolating the salt (Li, Na) by treatment with the alkali hydroxide or exchanging the sodium salt of tenatoprazole with Mg++ or Ca++ cation.