Abstract: A method and apparatus for performing multiple branch predictions per cycle is disclosed. The method and apparatus according to the present invention determine, within one fetch cycle, which instructions in a plurality of fetch instructions are branches and whether such branches are taken or not taken thereby finding the oldest taken branch, which has a target address that is fetched within the same fetch cycle.

Abstract: A method for repairing a pipeline in response to a branch instruction having a branch, includes the steps of providing a branch repair table having a plurality of entries, allocating an entry in the branch repair table for the branch instruction, storing a target address, a fall-through address, and repair information in the entry in the branch repair table, processing the branch instruction to determine whether the branch was taken, and repairing the pipeline in response to the repair information and the fall-through address in the entry in the branch repair table when the branch was not taken.

Abstract: A register allocator is provided including a plurality of N allocatable memory cells arranged in B banks having N/B rows each so that each of the N allocatable memory cells is capable of storing a register identifier. The register allocator includes a plurality of M parallel execution write data ports coupled to the plurality of N allocatable memory cells so as to be capable of writing a de-allocated register identifier to a first associated memory cell and a plurality of M parallel execution read data ports coupled to the plurality of N allocatable memory cells so as to be capable of reading an allocated register identifier from a second associated memory cell. The register allocator includes a plurality of M (N/B)-bit write enable ports coupled to the plurality of N allocatable memory cells by N/B 1-bit write entry ports and a plurality of M (N/B)-bit read enable ports coupled to the plurality of N allocatable memory cells by N/B 1-bit read entry ports. The register allocator also includes a decoded (B-.

Abstract: A microprocessor is provided with an instruction fetch mechanism that simultaneously predicts multiple control-flow instructions. The instruction fetch unit further is capable of handling multiple types of control-flow instructions. The instruction fetch unit uses predecode data and branch prediction data to select the next instruction fetch bundle address. If a branch misprediction is detected, a corrected branch target address is selected as the next fetch bundle address. If no branch misprediction occurs and the current fetch bundle includes a taken control-flow instruction, then the next fetch bundle address is selected based on the type of control-flow instruction detected. If the first taken control-flow instruction is a return instruction, a return address from the return address stack is selected as the next fetch bundle address.

Abstract: The outcome of a given branch instruction is predicted using early and late branch history addressing modes. In an early addressing process, a first subset of bits from a branch history register is used to first address a branch history table to obtain a plurality of candidate predictions. In a late addressing process, a second subset of bits from the branch history register is used to again address the branch history table to select one of the plurality of candidate predictions, the second subset of bits including additional branch history information loaded into the branch history register subsequent to the early addressing mode. In this way, more recent branch history information is used to predict the outcome of the given branch instruction.

Abstract: A microprocessor is provided with an instruction fetch mechanism that simultaneously predicts multiple control-flow instructions. The instruction fetch unit farther is capable of handling multiple types of control-flow instructions. The instruction fetch unit uses predecode data and branch prediction data to select the next instruction fetch bundle address. If a branch misprediction is detected, a corrected branch target address is selected as the next fetch bundle address. If no branch misprediction occurs and the current fetch bundle includes a taken control-flow instruction, then the next fetch bundle address is selected based on the type of control-flow instruction detected. If the first taken control-flow instruction is a return instruction, a return address from the return address stack is selected as the next fetch bundle address.

Abstract: The outcome of a given branch instruction is predicted using early and late branch history addressing modes. In an early addressing process, a first subset of bits from a branch history register is used to first address a branch history table to obtain a plurality of candidate predictions. In a late addressing process, a second subset of bits from the branch history register is used to again address the branch history table to select one of the plurality of candidate predictions, the second subset of bits including additional branch history information loaded into the branch history register subsequent to the early addressing mode. In this way, more recent branch history information is used to predict the outcome of the given branch instruction.