Patents by Inventor Ramesh Krishnamurthy
Ramesh Krishnamurthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11908718Abstract: Methods and apparatus for the in-situ measurement of metrology parameters are disclosed herein. Some embodiments of the disclosure further provide for the real-time adjustment of process parameters based on the measure metrology parameters. Some embodiments of the disclosure provide for a multi-stage processing chamber top plate with one or more sensors between process stations.Type: GrantFiled: February 22, 2022Date of Patent: February 20, 2024Assignee: Applied Materials, Inc.Inventors: Ramesh Krishnamurthy, Lakshmanan Karuppiah
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Patent number: 11853251Abstract: Disclosed are techniques for chip-to-chip (C2C) serial communications, such as communications between chiplets on a multi-chip package. In some aspects, a method of on-die monitoring of C2C links comprises detecting a change of the C2C link from a first link state to a second link state and storing link state change information in an on-die first-in, first-out (FIFO) buffer. The link state change information indicates the first link state, the duration of time the C2C link was in the first link state, and the speed of the C2C link in the first link state. Upon detecting a request for link state change information, link state change information is retrieved from the FIFO buffer and transmitted serially to an output pin of the die, such as a general purpose input/output (GPIO) pin.Type: GrantFiled: May 4, 2022Date of Patent: December 26, 2023Assignee: QUALCOMM IncorporatedInventors: Ramesh Krishnamurthy Madhira, Ibrahim Ouda, Kaushik Roychowdhury
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Publication number: 20230359579Abstract: Disclosed are techniques for chip-to-chip (C2C) serial communications, such as communications between chiplets on a multi-chip package. In some aspects, a method of on-die monitoring of C2C links comprises detecting a change of the C2C link from a first link state to a second link state and storing link state change information in an on-die first-in, first-out (FIFO) buffer. The link state change information indicates the first link state, the duration of time the C2C link was in the first link state, and the speed of the C2C link in the first link state. Upon detecting a request for link state change information, link state change information is retrieved from the FIFO buffer and transmitted serially to an output pin of the die, such as a general purpose input/output (GPIO) pin.Type: ApplicationFiled: May 4, 2022Publication date: November 9, 2023Inventors: Ramesh Krishnamurthy MADHIRA, Ibrahim OUDA, Kaushik ROYCHOWDHURY
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Publication number: 20230129824Abstract: Systems and methods for cloud federated token just in time authorization are disclosed. A method may include: (1) receiving, by a cloud authentication services computer program, authenticating information for a user from an active directory federation service computer program; (2) querying, by the cloud authentication services computer program, a plurality of backend services to validate the authenticating information; (3) communicating, by the cloud authentication services computer program, validation to the active directory federation service computer program, wherein the active directory federation service computer program is configured to generate a security token comprising one or more assertion, wherein the assertion comprises a limit on a session with the user at a cloud platform, and wherein the cloud platform is configured to receive the security token and a trusted federated endpoint executed by the cloud platform is configured to enforce the limit on the session.Type: ApplicationFiled: October 21, 2021Publication date: April 27, 2023Inventors: Kanishka HETTIARACHCHI, Ricky Hei Wong CHAN, Renfei ZHANG, Ross S INDYKE, Vijay Basker BALAKRISHNAN, Vladimir BELINKIS, Joseph SCHILLING, Ramesh KRISHNAMURTHY
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Publication number: 20220181179Abstract: Methods and apparatus for the in-situ measurement of metrology parameters are disclosed herein. Some embodiments of the disclosure further provide for the real-time adjustment of process parameters based on the measure metrology parameters. Some embodiments of the disclosure provide for a multi-stage processing chamber top plate with one or more sensors between process stations.Type: ApplicationFiled: February 22, 2022Publication date: June 9, 2022Applicant: Applied Materials, Inc.Inventors: Ramesh Krishnamurthy, Lakshmanan Karuppiah
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Patent number: 11289352Abstract: Methods and apparatus for the in-situ measurement of metrology parameters are disclosed herein. Some embodiments of the disclosure further provide for the real-time adjustment of process parameters based on the measure metrology parameters. Some embodiments of the disclosure provide for a multi-stage processing chamber top plate with one or more sensors between process stations.Type: GrantFiled: October 24, 2019Date of Patent: March 29, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Ramesh Krishnamurthy, Lakshmanan Karuppiah
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Patent number: 11165854Abstract: An embodiment of the present invention may be directed to large scale screen capturing on operating systems across global data center deployments. The system performs monitoring and recording activities, reporting and auditing the activities and further implementing an autonomous (agentless) deployment model. The system may orchestrate a number of agents to execute on an asynchronous basis to capture and aggregate screen data as well as identify associated metadata in real time. The system may also publish the aggregated screen data.Type: GrantFiled: April 22, 2020Date of Patent: November 2, 2021Assignee: JPMorgan Chase Bank, N.A.Inventors: Ramesh Krishnamurthy, Ricky Hei Wong Chan, Vijaya Basker Balakrishnan, Ross S. Indyke, Renfei Zhang, Kanishka Hettiarachchi
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Publication number: 20210337013Abstract: An embodiment of the present invention may be directed to performing monitoring and recording activities, reporting and auditing the activities and further implementing an autonomous (agentless) deployment model.Type: ApplicationFiled: April 22, 2020Publication date: October 28, 2021Inventors: Ramesh Krishnamurthy, Ricky Hei Wong Chan, Vijaya Basker Balakrishnan, Ross S. Indyke, Renfei Zhang, Kanishka Hettiarachchi
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Publication number: 20200335369Abstract: Methods and apparatus for the in-situ measurement of metrology parameters are disclosed herein. Some embodiments of the disclosure further provide for the real-time adjustment of process parameters based on the measure metrology parameters. Some embodiments of the disclosure provide for a multi-stage processing chamber top plate with one or more sensors between process stations.Type: ApplicationFiled: October 24, 2019Publication date: October 22, 2020Inventors: Ramesh Krishnamurthy, Lakshmanan Karuppiah
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Patent number: 9793132Abstract: Etch masks and methods of dicing semiconductor wafers are described. In an example, an etch mask for a wafer singulation process includes a water-soluble matrix based on a solid component and water. The etch mask also includes a plurality of particles dispersed throughout the water-soluble matrix. The plurality of particles has an average diameter approximately in the range of 5-100 nanometers. A ratio of weight % of the solid component to weight % of the plurality of particles is approximately in the range of 1:0.1-1:4.Type: GrantFiled: May 13, 2016Date of Patent: October 17, 2017Assignee: Applied Materials, Inc.Inventors: Wenguang Li, James S. Papanu, Ramesh Krishnamurthy, Prabhat Kumar, Brad Eaton, Ajay Kumar, Alexander N. Lerner
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Patent number: 7829243Abstract: A method for etching a chromium layer is provided herein. In one embodiment, a method for etching a chromium layer includes providing a filmstack in an etching chamber, the filmstack having a chromium layer partially exposed through a patterned layer, providing at least one halogen containing process gas to a processing chamber, biasing the layer disposed on a substrate support in the processing chamber with a plurality of power pulses less than 600 Watts, and etching the chromium layer through a patterned mask. The method for plasma etching a chromium layer described herein is particularly suitable for fabricating photomasks.Type: GrantFiled: January 27, 2005Date of Patent: November 9, 2010Assignee: Applied Materials, Inc.Inventors: Xiaoyi Chen, Michael Grimbergen, Madhavi Chandrachood, Jeffrey X. Tran, Ajay Kumar, Simon Tam, Ramesh Krishnamurthy
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Patent number: 7431795Abstract: A method and apparatus for process integration in manufacture of a gate structure of a field effect transistor are disclosed. The method includes assembling an integrated substrate processing system having a metrology module and a vacuumed processing platform to perform controlled and adaptive plasma processes without exposing the substrate to a non-vacuumed environment.Type: GrantFiled: July 29, 2004Date of Patent: October 7, 2008Assignee: Applied Materials, Inc.Inventors: Ajay Kumar, Ramesh Krishnamurthy
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Patent number: 7363534Abstract: A method and system for stateful switch-over in a high-availability point to point system is disclosed. The disclosed method includes in one embodiment detecting a change in state of a point to point link between a first peer data processing system and a second peer data processing system; storing state data for the point to point link with an active processor within the first peer data processing system in response to detecting the change in state; and transferring a copy of the state data to a standby processor within the first peer data processing system. The disclosed method includes in another embodiment, transferring data between the first peer data processing system and the second peer data processing system utilizing the active processor; detecting a switch-over condition; and transferring data between the first peer data processing system and the second peer data processing system utilizing the standby processor in response to detecting the switch-over condition.Type: GrantFiled: September 30, 2002Date of Patent: April 22, 2008Assignee: Cisco Technology, Inc.Inventors: Ramesh Krishnamurthy, Jeffrey D. Haag
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Patent number: 7354866Abstract: A method and apparatus for process integration in manufacture of a gate structure of a field effect transistor are disclosed. The method includes assembling an integrated substrate processing system having a metrology module and a vacuumed processing platform to perform controlled and adaptive plasma processes without exposing the substrate to a non-vacuumed environment.Type: GrantFiled: September 13, 2006Date of Patent: April 8, 2008Assignee: Applied Materials, Inc.Inventors: Ajay Kumar, Ramesh Krishnamurthy
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Publication number: 20070026547Abstract: A method and apparatus for process integration in manufacture of a gate structure of a field effect transistor are disclosed. The method includes assembling an integrated substrate processing system having a metrology module and a vacuumed processing platform to perform controlled and adaptive plasma processes without exposing the substrate to a non-vacuumed environment.Type: ApplicationFiled: September 13, 2006Publication date: February 1, 2007Applicant: Applied Materials, Inc.Inventors: Ajay Kumar, Ramesh Krishnamurthy
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Patent number: 7149224Abstract: The present invention defines a method to optimize PPP negotiations during a data communication session between two peer network elements in a network. During the configuration cycle of a PPP negotiation, the responding network element uses the option values of the first configuration request packet sent by the sending network element to predict the option values of the next configuration request packet that the sending network element will send. The responding network element then generates a response packet based on the predicted option values. The responding network element forwards the response packet before the next request packet is received from the sending network element. Once the response packets are forwarded, the internal states of the responding network element are set appropriately to initiate communication for the next protocol level.Type: GrantFiled: October 23, 2001Date of Patent: December 12, 2006Assignee: Cisco Technology, Inc.Inventor: Ramesh Krishnamurthy
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Publication number: 20060166107Abstract: A method for etching a chromium layer is provided herein. In one embodiment, a method for etching a chromium layer includes providing a filmstack in an etching chamber, the filmstack having a chromium layer partially exposed through a patterned layer, providing at least one halogen containing process gas to a processing chamber, biasing the layer disposed on a substrate support in the processing chamber with a plurality of power pulses less than 600 Watts, and etching the chromium layer through a patterned mask. The method for plasma etching a chromium layer described herein is particularly suitable for fabricating photomasks.Type: ApplicationFiled: January 27, 2005Publication date: July 27, 2006Inventors: Xiaoyi Chen, Michael Grimbergen, Madhavi Chandrachood, Jeffrey Tran, Ajay Kumar, Simon Tam, Ramesh Krishnamurthy
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Publication number: 20060021702Abstract: A method and apparatus for process integration in manufacture of a gate structure of a field effect transistor are disclosed. The method includes assembling an integrated substrate processing system having a metrology module and a vacuumed processing platform to perform controlled and adaptive plasma processes without exposing the substrate to a non-vacuumed environment.Type: ApplicationFiled: July 29, 2004Publication date: February 2, 2006Inventors: Ajay Kumar, Ramesh Krishnamurthy